clk-mt2712-mfg.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt2712-clk.h>
  11. static const struct mtk_gate_regs mfg_cg_regs = {
  12. .set_ofs = 0x4,
  13. .clr_ofs = 0x8,
  14. .sta_ofs = 0x0,
  15. };
  16. #define GATE_MFG(_id, _name, _parent, _shift) { \
  17. .id = _id, \
  18. .name = _name, \
  19. .parent_name = _parent, \
  20. .regs = &mfg_cg_regs, \
  21. .shift = _shift, \
  22. .ops = &mtk_clk_gate_ops_setclr, \
  23. }
  24. static const struct mtk_gate mfg_clks[] = {
  25. GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
  26. };
  27. static int clk_mt2712_mfg_probe(struct platform_device *pdev)
  28. {
  29. struct clk_onecell_data *clk_data;
  30. int r;
  31. struct device_node *node = pdev->dev.of_node;
  32. clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
  33. mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
  34. clk_data);
  35. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  36. if (r != 0)
  37. pr_err("%s(): could not register clock provider: %d\n",
  38. __func__, r);
  39. return r;
  40. }
  41. static const struct of_device_id of_match_clk_mt2712_mfg[] = {
  42. { .compatible = "mediatek,mt2712-mfgcfg", },
  43. {}
  44. };
  45. static struct platform_driver clk_mt2712_mfg_drv = {
  46. .probe = clk_mt2712_mfg_probe,
  47. .driver = {
  48. .name = "clk-mt2712-mfg",
  49. .of_match_table = of_match_clk_mt2712_mfg,
  50. },
  51. };
  52. builtin_platform_driver(clk_mt2712_mfg_drv);