clk-mt2712-bdp.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt2712-clk.h>
  11. static const struct mtk_gate_regs bdp_cg_regs = {
  12. .set_ofs = 0x100,
  13. .clr_ofs = 0x100,
  14. .sta_ofs = 0x100,
  15. };
  16. #define GATE_BDP(_id, _name, _parent, _shift) { \
  17. .id = _id, \
  18. .name = _name, \
  19. .parent_name = _parent, \
  20. .regs = &bdp_cg_regs, \
  21. .shift = _shift, \
  22. .ops = &mtk_clk_gate_ops_no_setclr, \
  23. }
  24. static const struct mtk_gate bdp_clks[] = {
  25. GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
  26. GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
  27. GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
  28. GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
  29. GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
  30. GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
  31. GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
  32. GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
  33. GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
  34. GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
  35. GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
  36. GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
  37. GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
  38. GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
  39. GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
  40. GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
  41. GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
  42. GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
  43. GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
  44. GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
  45. GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
  46. GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
  47. GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
  48. GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
  49. GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
  50. GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
  51. GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
  52. GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
  53. };
  54. static int clk_mt2712_bdp_probe(struct platform_device *pdev)
  55. {
  56. struct clk_onecell_data *clk_data;
  57. int r;
  58. struct device_node *node = pdev->dev.of_node;
  59. clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
  60. mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
  61. clk_data);
  62. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  63. if (r != 0)
  64. pr_err("%s(): could not register clock provider: %d\n",
  65. __func__, r);
  66. return r;
  67. }
  68. static const struct of_device_id of_match_clk_mt2712_bdp[] = {
  69. { .compatible = "mediatek,mt2712-bdpsys", },
  70. {}
  71. };
  72. static struct platform_driver clk_mt2712_bdp_drv = {
  73. .probe = clk_mt2712_bdp_probe,
  74. .driver = {
  75. .name = "clk-mt2712-bdp",
  76. .of_match_table = of_match_clk_mt2712_bdp,
  77. },
  78. };
  79. builtin_platform_driver(clk_mt2712_bdp_drv);