clk-mt2701.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Shunli Wang <shunli.wang@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include "clk-mtk.h"
  12. #include "clk-gate.h"
  13. #include "clk-cpumux.h"
  14. #include <dt-bindings/clock/mt2701-clk.h>
  15. /*
  16. * For some clocks, we don't care what their actual rates are. And these
  17. * clocks may change their rate on different products or different scenarios.
  18. * So we model these clocks' rate as 0, to denote it's not an actual rate.
  19. */
  20. #define DUMMY_RATE 0
  21. static DEFINE_SPINLOCK(mt2701_clk_lock);
  22. static const struct mtk_fixed_clk top_fixed_clks[] = {
  23. FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
  24. 108 * MHZ),
  25. FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
  26. 400 * MHZ),
  27. FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
  28. 295750000),
  29. FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
  30. 340 * MHZ),
  31. FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
  32. 340 * MHZ),
  33. FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
  34. 340 * MHZ),
  35. FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
  36. 27 * MHZ),
  37. FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
  38. 416 * MHZ),
  39. FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
  40. 143 * MHZ),
  41. FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
  42. 27 * MHZ),
  43. FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
  44. DUMMY_RATE),
  45. FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
  46. DUMMY_RATE),
  47. FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
  48. DUMMY_RATE),
  49. };
  50. static const struct mtk_fixed_factor top_fixed_divs[] = {
  51. FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
  52. FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  53. FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  54. FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  55. FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  56. FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  57. FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  58. FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  59. FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  60. FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  61. FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  62. FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  63. FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  64. FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  65. FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  66. FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  67. FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
  68. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  69. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  70. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  71. FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  72. FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
  73. FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
  74. FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
  75. FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
  76. FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  77. FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  78. FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
  79. FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
  80. FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
  81. FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
  82. FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
  83. FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
  84. FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
  85. FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
  86. FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
  87. FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
  88. FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
  89. FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  90. FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
  91. FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
  92. FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
  93. FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  94. FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
  95. FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
  96. FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
  97. FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
  98. FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
  99. FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
  100. FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
  101. FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
  102. FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
  103. FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
  104. FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
  105. FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
  106. FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
  107. FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
  108. FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
  109. FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
  110. FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
  111. FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
  112. FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
  113. FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
  114. FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
  115. FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
  116. FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
  117. FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
  118. FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
  119. FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
  120. FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
  121. FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
  122. FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
  123. FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
  124. };
  125. static const char * const axi_parents[] = {
  126. "clk26m",
  127. "syspll1_d2",
  128. "syspll_d5",
  129. "syspll1_d4",
  130. "univpll_d5",
  131. "univpll2_d2",
  132. "mmpll_d2",
  133. "dmpll_d2"
  134. };
  135. static const char * const mem_parents[] = {
  136. "clk26m",
  137. "dmpll_ck"
  138. };
  139. static const char * const ddrphycfg_parents[] = {
  140. "clk26m",
  141. "syspll1_d8"
  142. };
  143. static const char * const mm_parents[] = {
  144. "clk26m",
  145. "vencpll_ck",
  146. "syspll1_d2",
  147. "syspll1_d4",
  148. "univpll_d5",
  149. "univpll1_d2",
  150. "univpll2_d2",
  151. "dmpll_ck"
  152. };
  153. static const char * const pwm_parents[] = {
  154. "clk26m",
  155. "univpll2_d4",
  156. "univpll3_d2",
  157. "univpll1_d4",
  158. };
  159. static const char * const vdec_parents[] = {
  160. "clk26m",
  161. "vdecpll_ck",
  162. "syspll_d5",
  163. "syspll1_d4",
  164. "univpll_d5",
  165. "univpll2_d2",
  166. "vencpll_ck",
  167. "msdcpll_d2",
  168. "mmpll_d2"
  169. };
  170. static const char * const mfg_parents[] = {
  171. "clk26m",
  172. "mmpll_ck",
  173. "dmpll_x2_ck",
  174. "msdcpll_ck",
  175. "clk26m",
  176. "syspll_d3",
  177. "univpll_d3",
  178. "univpll1_d2"
  179. };
  180. static const char * const camtg_parents[] = {
  181. "clk26m",
  182. "univpll_d26",
  183. "univpll2_d2",
  184. "syspll3_d2",
  185. "syspll3_d4",
  186. "msdcpll_d2",
  187. "mmpll_d2"
  188. };
  189. static const char * const uart_parents[] = {
  190. "clk26m",
  191. "univpll2_d8"
  192. };
  193. static const char * const spi_parents[] = {
  194. "clk26m",
  195. "syspll3_d2",
  196. "syspll4_d2",
  197. "univpll2_d4",
  198. "univpll1_d8"
  199. };
  200. static const char * const usb20_parents[] = {
  201. "clk26m",
  202. "univpll1_d8",
  203. "univpll3_d4"
  204. };
  205. static const char * const msdc30_parents[] = {
  206. "clk26m",
  207. "msdcpll_d2",
  208. "syspll2_d2",
  209. "syspll1_d4",
  210. "univpll1_d4",
  211. "univpll2_d4"
  212. };
  213. static const char * const aud_intbus_parents[] = {
  214. "clk26m",
  215. "syspll1_d4",
  216. "syspll3_d2",
  217. "syspll4_d2",
  218. "univpll3_d2",
  219. "univpll2_d4"
  220. };
  221. static const char * const pmicspi_parents[] = {
  222. "clk26m",
  223. "syspll1_d8",
  224. "syspll2_d4",
  225. "syspll4_d2",
  226. "syspll3_d4",
  227. "syspll2_d8",
  228. "syspll1_d16",
  229. "univpll3_d4",
  230. "univpll_d26",
  231. "dmpll_d2",
  232. "dmpll_d4"
  233. };
  234. static const char * const scp_parents[] = {
  235. "clk26m",
  236. "syspll1_d8",
  237. "dmpll_d2",
  238. "dmpll_d4"
  239. };
  240. static const char * const dpi0_parents[] = {
  241. "clk26m",
  242. "mipipll",
  243. "mipipll_d2",
  244. "mipipll_d4",
  245. "clk26m",
  246. "tvdpll_ck",
  247. "tvdpll_d2",
  248. "tvdpll_d4"
  249. };
  250. static const char * const dpi1_parents[] = {
  251. "clk26m",
  252. "tvdpll_ck",
  253. "tvdpll_d2",
  254. "tvdpll_d4"
  255. };
  256. static const char * const tve_parents[] = {
  257. "clk26m",
  258. "mipipll",
  259. "mipipll_d2",
  260. "mipipll_d4",
  261. "clk26m",
  262. "tvdpll_ck",
  263. "tvdpll_d2",
  264. "tvdpll_d4"
  265. };
  266. static const char * const hdmi_parents[] = {
  267. "clk26m",
  268. "hdmipll_ck",
  269. "hdmipll_d2",
  270. "hdmipll_d3"
  271. };
  272. static const char * const apll_parents[] = {
  273. "clk26m",
  274. "audpll",
  275. "audpll_d4",
  276. "audpll_d8",
  277. "audpll_d16",
  278. "audpll_d24",
  279. "clk26m",
  280. "clk26m"
  281. };
  282. static const char * const rtc_parents[] = {
  283. "32k_internal",
  284. "32k_external",
  285. "clk26m",
  286. "univpll3_d8"
  287. };
  288. static const char * const nfi2x_parents[] = {
  289. "clk26m",
  290. "syspll2_d2",
  291. "syspll_d7",
  292. "univpll3_d2",
  293. "syspll2_d4",
  294. "univpll3_d4",
  295. "syspll4_d4",
  296. "clk26m"
  297. };
  298. static const char * const emmc_hclk_parents[] = {
  299. "clk26m",
  300. "syspll1_d2",
  301. "syspll1_d4",
  302. "syspll2_d2"
  303. };
  304. static const char * const flash_parents[] = {
  305. "clk26m_d8",
  306. "clk26m",
  307. "syspll2_d8",
  308. "syspll3_d4",
  309. "univpll3_d4",
  310. "syspll4_d2",
  311. "syspll2_d4",
  312. "univpll2_d4"
  313. };
  314. static const char * const di_parents[] = {
  315. "clk26m",
  316. "tvd2pll_ck",
  317. "tvd2pll_d2",
  318. "clk26m"
  319. };
  320. static const char * const nr_osd_parents[] = {
  321. "clk26m",
  322. "vencpll_ck",
  323. "syspll1_d2",
  324. "syspll1_d4",
  325. "univpll_d5",
  326. "univpll1_d2",
  327. "univpll2_d2",
  328. "dmpll_ck"
  329. };
  330. static const char * const hdmirx_bist_parents[] = {
  331. "clk26m",
  332. "syspll_d3",
  333. "clk26m",
  334. "syspll1_d16",
  335. "syspll4_d2",
  336. "syspll1_d4",
  337. "vencpll_ck",
  338. "clk26m"
  339. };
  340. static const char * const intdir_parents[] = {
  341. "clk26m",
  342. "mmpll_ck",
  343. "syspll_d2",
  344. "univpll_d2"
  345. };
  346. static const char * const asm_parents[] = {
  347. "clk26m",
  348. "univpll2_d4",
  349. "univpll2_d2",
  350. "syspll_d5"
  351. };
  352. static const char * const ms_card_parents[] = {
  353. "clk26m",
  354. "univpll3_d8",
  355. "syspll4_d4"
  356. };
  357. static const char * const ethif_parents[] = {
  358. "clk26m",
  359. "syspll1_d2",
  360. "syspll_d5",
  361. "syspll1_d4",
  362. "univpll_d5",
  363. "univpll1_d2",
  364. "dmpll_ck",
  365. "dmpll_d2"
  366. };
  367. static const char * const hdmirx_parents[] = {
  368. "clk26m",
  369. "univpll_d52"
  370. };
  371. static const char * const cmsys_parents[] = {
  372. "clk26m",
  373. "syspll1_d2",
  374. "univpll1_d2",
  375. "univpll_d5",
  376. "syspll_d5",
  377. "syspll2_d2",
  378. "syspll1_d4",
  379. "syspll3_d2",
  380. "syspll2_d4",
  381. "syspll1_d8",
  382. "clk26m",
  383. "clk26m",
  384. "clk26m",
  385. "clk26m",
  386. "clk26m"
  387. };
  388. static const char * const clk_8bdac_parents[] = {
  389. "32k_internal",
  390. "8bdac_ck",
  391. "clk26m",
  392. "clk26m"
  393. };
  394. static const char * const aud2dvd_parents[] = {
  395. "a1sys_hp_ck",
  396. "a2sys_hp_ck"
  397. };
  398. static const char * const padmclk_parents[] = {
  399. "clk26m",
  400. "univpll_d26",
  401. "univpll_d52",
  402. "univpll_d108",
  403. "univpll2_d8",
  404. "univpll2_d16",
  405. "univpll2_d32"
  406. };
  407. static const char * const aud_mux_parents[] = {
  408. "clk26m",
  409. "aud1pll_98m_ck",
  410. "aud2pll_90m_ck",
  411. "hadds2pll_98m",
  412. "audio_ext1_ck",
  413. "audio_ext2_ck"
  414. };
  415. static const char * const aud_src_parents[] = {
  416. "aud_mux1_sel",
  417. "aud_mux2_sel"
  418. };
  419. static const char * const cpu_parents[] = {
  420. "clk26m",
  421. "armpll",
  422. "mainpll",
  423. "mmpll"
  424. };
  425. static const struct mtk_composite cpu_muxes[] __initconst = {
  426. MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
  427. };
  428. static const struct mtk_composite top_muxes[] = {
  429. MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
  430. 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
  431. MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
  432. 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
  433. MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
  434. ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
  435. MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
  436. 0x0040, 24, 3, 31),
  437. MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
  438. 0x0050, 0, 2, 7),
  439. MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
  440. 0x0050, 8, 4, 15),
  441. MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
  442. 0x0050, 16, 3, 23),
  443. MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
  444. 0x0050, 24, 3, 31),
  445. MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
  446. 0x0060, 0, 1, 7),
  447. MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
  448. 0x0060, 8, 3, 15),
  449. MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
  450. 0x0060, 16, 2, 23),
  451. MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
  452. 0x0060, 24, 3, 31),
  453. MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
  454. 0x0070, 0, 3, 7),
  455. MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
  456. 0x0070, 8, 3, 15),
  457. MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
  458. 0x0070, 16, 1, 23),
  459. MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
  460. 0x0070, 24, 3, 31),
  461. MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
  462. 0x0080, 0, 4, 7),
  463. MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
  464. 0x0080, 8, 2, 15),
  465. MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
  466. 0x0080, 16, 3, 23),
  467. MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
  468. 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
  469. MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
  470. 0x0090, 0, 3, 7),
  471. MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
  472. 0x0090, 8, 2, 15),
  473. MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
  474. 0x0090, 16, 3, 23),
  475. MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
  476. 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
  477. MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
  478. 0x00A0, 8, 3, 15),
  479. MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
  480. 0x00A0, 24, 2, 31),
  481. MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
  482. 0x00B0, 0, 3, 7),
  483. MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
  484. 0x00B0, 8, 2, 15),
  485. MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
  486. 0x00B0, 16, 3, 23),
  487. MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
  488. 0x00B0, 24, 3, 31),
  489. MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
  490. hdmirx_bist_parents, 0x00C0, 0, 3, 7),
  491. MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
  492. 0x00C0, 8, 2, 15),
  493. MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
  494. 0x00C0, 16, 2, 23),
  495. MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
  496. 0x00C0, 24, 3, 31),
  497. MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
  498. 0x00D0, 0, 2, 7),
  499. MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
  500. 0x00D0, 16, 2, 23),
  501. MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
  502. 0x00D0, 24, 3, 31),
  503. MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
  504. 0x00E0, 0, 1, 7),
  505. MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
  506. 0x00E0, 8, 3, 15),
  507. MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
  508. 0x00E0, 16, 4, 23),
  509. MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
  510. 0x00E0, 24, 3, 31),
  511. MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
  512. 0x00F0, 0, 3, 7),
  513. MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
  514. 0x00F0, 8, 2, 15),
  515. MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
  516. 0x00F0, 16, 1, 23),
  517. MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
  518. 0x0100, 0, 3),
  519. MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
  520. 0x012c, 0, 3),
  521. MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
  522. 0x012c, 3, 3),
  523. MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
  524. 0x012c, 6, 3),
  525. MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
  526. 0x012c, 15, 1, 23),
  527. MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
  528. 0x012c, 16, 1, 24),
  529. MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
  530. 0x012c, 17, 1, 25),
  531. MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
  532. 0x012c, 18, 1, 26),
  533. MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
  534. 0x012c, 19, 1, 27),
  535. MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
  536. 0x012c, 20, 1, 28),
  537. };
  538. static const struct mtk_clk_divider top_adj_divs[] = {
  539. DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
  540. 0x0120, 0, 8),
  541. DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
  542. 0x0120, 8, 8),
  543. DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
  544. 0x0120, 16, 8),
  545. DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
  546. 0x0120, 24, 8),
  547. DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
  548. 0x0124, 0, 8),
  549. DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
  550. 0x0124, 8, 8),
  551. DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
  552. 0x0124, 16, 8),
  553. DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
  554. 0x0124, 24, 8),
  555. DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
  556. 0x0128, 0, 8),
  557. DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
  558. 0x0128, 8, 8),
  559. };
  560. static const struct mtk_gate_regs top_aud_cg_regs = {
  561. .sta_ofs = 0x012C,
  562. };
  563. #define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
  564. .id = _id, \
  565. .name = _name, \
  566. .parent_name = _parent, \
  567. .regs = &top_aud_cg_regs, \
  568. .shift = _shift, \
  569. .ops = &mtk_clk_gate_ops_no_setclr, \
  570. }
  571. static const struct mtk_gate top_clks[] = {
  572. GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
  573. 21),
  574. GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
  575. 22),
  576. GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
  577. 23),
  578. GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
  579. 24),
  580. GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
  581. 25),
  582. GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
  583. 26),
  584. GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
  585. 27),
  586. GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
  587. 28),
  588. };
  589. static int mtk_topckgen_init(struct platform_device *pdev)
  590. {
  591. struct clk_onecell_data *clk_data;
  592. void __iomem *base;
  593. struct device_node *node = pdev->dev.of_node;
  594. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  595. base = devm_ioremap_resource(&pdev->dev, res);
  596. if (IS_ERR(base))
  597. return PTR_ERR(base);
  598. clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
  599. mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  600. clk_data);
  601. mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
  602. clk_data);
  603. mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
  604. base, &mt2701_clk_lock, clk_data);
  605. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
  606. base, &mt2701_clk_lock, clk_data);
  607. mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  608. clk_data);
  609. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  610. }
  611. static const struct mtk_gate_regs infra_cg_regs = {
  612. .set_ofs = 0x0040,
  613. .clr_ofs = 0x0044,
  614. .sta_ofs = 0x0048,
  615. };
  616. #define GATE_ICG(_id, _name, _parent, _shift) { \
  617. .id = _id, \
  618. .name = _name, \
  619. .parent_name = _parent, \
  620. .regs = &infra_cg_regs, \
  621. .shift = _shift, \
  622. .ops = &mtk_clk_gate_ops_setclr, \
  623. }
  624. static const struct mtk_gate infra_clks[] = {
  625. GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
  626. GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
  627. GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
  628. GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
  629. GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
  630. GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
  631. GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
  632. GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
  633. GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
  634. GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
  635. GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
  636. GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
  637. GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
  638. GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
  639. GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
  640. GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
  641. GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
  642. GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
  643. };
  644. static const struct mtk_fixed_factor infra_fixed_divs[] = {
  645. FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
  646. };
  647. static struct clk_onecell_data *infra_clk_data;
  648. static void __init mtk_infrasys_init_early(struct device_node *node)
  649. {
  650. int r, i;
  651. if (!infra_clk_data) {
  652. infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
  653. for (i = 0; i < CLK_INFRA_NR; i++)
  654. infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
  655. }
  656. mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
  657. infra_clk_data);
  658. mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
  659. infra_clk_data);
  660. r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
  661. if (r)
  662. pr_err("%s(): could not register clock provider: %d\n",
  663. __func__, r);
  664. }
  665. CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
  666. mtk_infrasys_init_early);
  667. static int mtk_infrasys_init(struct platform_device *pdev)
  668. {
  669. int r, i;
  670. struct device_node *node = pdev->dev.of_node;
  671. if (!infra_clk_data) {
  672. infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
  673. } else {
  674. for (i = 0; i < CLK_INFRA_NR; i++) {
  675. if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
  676. infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
  677. }
  678. }
  679. mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  680. infra_clk_data);
  681. mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
  682. infra_clk_data);
  683. r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
  684. if (r)
  685. return r;
  686. mtk_register_reset_controller(node, 2, 0x30);
  687. return 0;
  688. }
  689. static const struct mtk_gate_regs peri0_cg_regs = {
  690. .set_ofs = 0x0008,
  691. .clr_ofs = 0x0010,
  692. .sta_ofs = 0x0018,
  693. };
  694. static const struct mtk_gate_regs peri1_cg_regs = {
  695. .set_ofs = 0x000c,
  696. .clr_ofs = 0x0014,
  697. .sta_ofs = 0x001c,
  698. };
  699. #define GATE_PERI0(_id, _name, _parent, _shift) { \
  700. .id = _id, \
  701. .name = _name, \
  702. .parent_name = _parent, \
  703. .regs = &peri0_cg_regs, \
  704. .shift = _shift, \
  705. .ops = &mtk_clk_gate_ops_setclr, \
  706. }
  707. #define GATE_PERI1(_id, _name, _parent, _shift) { \
  708. .id = _id, \
  709. .name = _name, \
  710. .parent_name = _parent, \
  711. .regs = &peri1_cg_regs, \
  712. .shift = _shift, \
  713. .ops = &mtk_clk_gate_ops_setclr, \
  714. }
  715. static const struct mtk_gate peri_clks[] = {
  716. GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
  717. GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
  718. GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
  719. GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
  720. GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
  721. GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
  722. GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
  723. GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
  724. GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
  725. GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
  726. GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
  727. GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
  728. GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
  729. GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
  730. GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
  731. GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
  732. GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
  733. GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
  734. GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
  735. GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
  736. GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
  737. GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
  738. GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
  739. GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
  740. GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
  741. GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
  742. GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
  743. GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
  744. GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
  745. GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
  746. GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
  747. GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
  748. GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
  749. GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
  750. GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
  751. GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
  752. GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
  753. GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
  754. GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
  755. GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
  756. GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
  757. GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
  758. GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
  759. GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
  760. };
  761. static const char * const uart_ck_sel_parents[] = {
  762. "clk26m",
  763. "uart_sel",
  764. };
  765. static const struct mtk_composite peri_muxs[] = {
  766. MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
  767. 0x40c, 0, 1),
  768. MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
  769. 0x40c, 1, 1),
  770. MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
  771. 0x40c, 2, 1),
  772. MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
  773. 0x40c, 3, 1),
  774. };
  775. static int mtk_pericfg_init(struct platform_device *pdev)
  776. {
  777. struct clk_onecell_data *clk_data;
  778. void __iomem *base;
  779. int r;
  780. struct device_node *node = pdev->dev.of_node;
  781. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  782. base = devm_ioremap_resource(&pdev->dev, res);
  783. if (IS_ERR(base))
  784. return PTR_ERR(base);
  785. clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
  786. mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  787. clk_data);
  788. mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
  789. &mt2701_clk_lock, clk_data);
  790. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  791. if (r)
  792. return r;
  793. mtk_register_reset_controller(node, 2, 0x0);
  794. return 0;
  795. }
  796. #define MT8590_PLL_FMAX (2000 * MHZ)
  797. #define CON0_MT8590_RST_BAR BIT(27)
  798. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
  799. _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
  800. .id = _id, \
  801. .name = _name, \
  802. .reg = _reg, \
  803. .pwr_reg = _pwr_reg, \
  804. .en_mask = _en_mask, \
  805. .flags = _flags, \
  806. .rst_bar_mask = CON0_MT8590_RST_BAR, \
  807. .fmax = MT8590_PLL_FMAX, \
  808. .pcwbits = _pcwbits, \
  809. .pd_reg = _pd_reg, \
  810. .pd_shift = _pd_shift, \
  811. .tuner_reg = _tuner_reg, \
  812. .pcw_reg = _pcw_reg, \
  813. .pcw_shift = _pcw_shift, \
  814. }
  815. static const struct mtk_pll_data apmixed_plls[] = {
  816. PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
  817. PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
  818. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
  819. HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
  820. PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
  821. HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
  822. PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
  823. 21, 0x230, 4, 0x0, 0x234, 0),
  824. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
  825. 21, 0x240, 4, 0x0, 0x244, 0),
  826. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
  827. 21, 0x250, 4, 0x0, 0x254, 0),
  828. PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
  829. 31, 0x270, 4, 0x0, 0x274, 0),
  830. PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
  831. 31, 0x280, 4, 0x0, 0x284, 0),
  832. PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
  833. 31, 0x290, 4, 0x0, 0x294, 0),
  834. PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
  835. 31, 0x2a0, 4, 0x0, 0x2a4, 0),
  836. PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
  837. 31, 0x2b0, 4, 0x0, 0x2b4, 0),
  838. PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
  839. 31, 0x2c0, 4, 0x0, 0x2c4, 0),
  840. PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
  841. 21, 0x2d0, 4, 0x0, 0x2d4, 0),
  842. };
  843. static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
  844. FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
  845. };
  846. static int mtk_apmixedsys_init(struct platform_device *pdev)
  847. {
  848. struct clk_onecell_data *clk_data;
  849. struct device_node *node = pdev->dev.of_node;
  850. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
  851. if (!clk_data)
  852. return -ENOMEM;
  853. mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
  854. clk_data);
  855. mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
  856. clk_data);
  857. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  858. }
  859. static const struct of_device_id of_match_clk_mt2701[] = {
  860. {
  861. .compatible = "mediatek,mt2701-topckgen",
  862. .data = mtk_topckgen_init,
  863. }, {
  864. .compatible = "mediatek,mt2701-infracfg",
  865. .data = mtk_infrasys_init,
  866. }, {
  867. .compatible = "mediatek,mt2701-pericfg",
  868. .data = mtk_pericfg_init,
  869. }, {
  870. .compatible = "mediatek,mt2701-apmixedsys",
  871. .data = mtk_apmixedsys_init,
  872. }, {
  873. /* sentinel */
  874. }
  875. };
  876. static int clk_mt2701_probe(struct platform_device *pdev)
  877. {
  878. int (*clk_init)(struct platform_device *);
  879. int r;
  880. clk_init = of_device_get_match_data(&pdev->dev);
  881. if (!clk_init)
  882. return -EINVAL;
  883. r = clk_init(pdev);
  884. if (r)
  885. dev_err(&pdev->dev,
  886. "could not register clock provider: %s: %d\n",
  887. pdev->name, r);
  888. return r;
  889. }
  890. static struct platform_driver clk_mt2701_drv = {
  891. .probe = clk_mt2701_probe,
  892. .driver = {
  893. .name = "clk-mt2701",
  894. .of_match_table = of_match_clk_mt2701,
  895. },
  896. };
  897. static int __init clk_mt2701_init(void)
  898. {
  899. return platform_driver_register(&clk_mt2701_drv);
  900. }
  901. arch_initcall(clk_mt2701_init);