clk-mt2701-mm.c 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Shunli Wang <shunli.wang@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt2701-clk.h>
  11. static const struct mtk_gate_regs disp0_cg_regs = {
  12. .set_ofs = 0x0104,
  13. .clr_ofs = 0x0108,
  14. .sta_ofs = 0x0100,
  15. };
  16. static const struct mtk_gate_regs disp1_cg_regs = {
  17. .set_ofs = 0x0114,
  18. .clr_ofs = 0x0118,
  19. .sta_ofs = 0x0110,
  20. };
  21. #define GATE_DISP0(_id, _name, _parent, _shift) { \
  22. .id = _id, \
  23. .name = _name, \
  24. .parent_name = _parent, \
  25. .regs = &disp0_cg_regs, \
  26. .shift = _shift, \
  27. .ops = &mtk_clk_gate_ops_setclr, \
  28. }
  29. #define GATE_DISP1(_id, _name, _parent, _shift) { \
  30. .id = _id, \
  31. .name = _name, \
  32. .parent_name = _parent, \
  33. .regs = &disp1_cg_regs, \
  34. .shift = _shift, \
  35. .ops = &mtk_clk_gate_ops_setclr, \
  36. }
  37. static const struct mtk_gate mm_clks[] = {
  38. GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
  39. GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
  40. GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
  41. GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
  42. GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
  43. GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
  44. GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
  45. GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
  46. GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
  47. GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
  48. GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
  49. GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
  50. GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
  51. GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
  52. GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
  53. GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15),
  54. GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
  55. GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
  56. GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
  57. GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
  58. GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
  59. GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
  60. GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1),
  61. GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
  62. GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
  63. GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
  64. GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
  65. GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
  66. GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
  67. GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
  68. GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
  69. GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
  70. GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
  71. GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
  72. };
  73. static int clk_mt2701_mm_probe(struct platform_device *pdev)
  74. {
  75. struct device *dev = &pdev->dev;
  76. struct device_node *node = dev->parent->of_node;
  77. struct clk_onecell_data *clk_data;
  78. int r;
  79. clk_data = mtk_alloc_clk_data(CLK_MM_NR);
  80. mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
  81. clk_data);
  82. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  83. if (r)
  84. dev_err(&pdev->dev,
  85. "could not register clock provider: %s: %d\n",
  86. pdev->name, r);
  87. return r;
  88. }
  89. static struct platform_driver clk_mt2701_mm_drv = {
  90. .probe = clk_mt2701_mm_probe,
  91. .driver = {
  92. .name = "clk-mt2701-mm",
  93. },
  94. };
  95. builtin_platform_driver(clk_mt2701_mm_drv);