clk-mt2701-bdp.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Shunli Wang <shunli.wang@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt2701-clk.h>
  11. static const struct mtk_gate_regs bdp0_cg_regs = {
  12. .set_ofs = 0x0104,
  13. .clr_ofs = 0x0108,
  14. .sta_ofs = 0x0100,
  15. };
  16. static const struct mtk_gate_regs bdp1_cg_regs = {
  17. .set_ofs = 0x0114,
  18. .clr_ofs = 0x0118,
  19. .sta_ofs = 0x0110,
  20. };
  21. #define GATE_BDP0(_id, _name, _parent, _shift) { \
  22. .id = _id, \
  23. .name = _name, \
  24. .parent_name = _parent, \
  25. .regs = &bdp0_cg_regs, \
  26. .shift = _shift, \
  27. .ops = &mtk_clk_gate_ops_setclr_inv, \
  28. }
  29. #define GATE_BDP1(_id, _name, _parent, _shift) { \
  30. .id = _id, \
  31. .name = _name, \
  32. .parent_name = _parent, \
  33. .regs = &bdp1_cg_regs, \
  34. .shift = _shift, \
  35. .ops = &mtk_clk_gate_ops_setclr_inv, \
  36. }
  37. static const struct mtk_gate bdp_clks[] = {
  38. GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
  39. GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
  40. GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
  41. GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
  42. GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
  43. GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
  44. GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
  45. GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
  46. GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
  47. GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
  48. GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
  49. GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
  50. GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
  51. GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
  52. GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
  53. GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
  54. GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
  55. GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
  56. GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
  57. GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
  58. GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
  59. GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
  60. GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
  61. GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
  62. GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
  63. GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
  64. GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
  65. GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
  66. GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
  67. GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
  68. GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
  69. GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
  70. GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
  71. GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
  72. GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
  73. GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
  74. GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
  75. GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
  76. GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
  77. GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
  78. GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
  79. GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
  80. GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
  81. GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
  82. GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
  83. GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
  84. GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
  85. GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
  86. GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
  87. };
  88. static const struct of_device_id of_match_clk_mt2701_bdp[] = {
  89. { .compatible = "mediatek,mt2701-bdpsys", },
  90. {}
  91. };
  92. static int clk_mt2701_bdp_probe(struct platform_device *pdev)
  93. {
  94. struct clk_onecell_data *clk_data;
  95. int r;
  96. struct device_node *node = pdev->dev.of_node;
  97. clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
  98. mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
  99. clk_data);
  100. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  101. if (r)
  102. dev_err(&pdev->dev,
  103. "could not register clock provider: %s: %d\n",
  104. pdev->name, r);
  105. return r;
  106. }
  107. static struct platform_driver clk_mt2701_bdp_drv = {
  108. .probe = clk_mt2701_bdp_probe,
  109. .driver = {
  110. .name = "clk-mt2701-bdp",
  111. .of_match_table = of_match_clk_mt2701_bdp,
  112. },
  113. };
  114. builtin_platform_driver(clk_mt2701_bdp_drv);