clk-mt2701-aud.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include "clk-mtk.h"
  12. #include "clk-gate.h"
  13. #include <dt-bindings/clock/mt2701-clk.h>
  14. #define GATE_AUDIO0(_id, _name, _parent, _shift) { \
  15. .id = _id, \
  16. .name = _name, \
  17. .parent_name = _parent, \
  18. .regs = &audio0_cg_regs, \
  19. .shift = _shift, \
  20. .ops = &mtk_clk_gate_ops_no_setclr, \
  21. }
  22. #define GATE_AUDIO1(_id, _name, _parent, _shift) { \
  23. .id = _id, \
  24. .name = _name, \
  25. .parent_name = _parent, \
  26. .regs = &audio1_cg_regs, \
  27. .shift = _shift, \
  28. .ops = &mtk_clk_gate_ops_no_setclr, \
  29. }
  30. #define GATE_AUDIO2(_id, _name, _parent, _shift) { \
  31. .id = _id, \
  32. .name = _name, \
  33. .parent_name = _parent, \
  34. .regs = &audio2_cg_regs, \
  35. .shift = _shift, \
  36. .ops = &mtk_clk_gate_ops_no_setclr, \
  37. }
  38. #define GATE_AUDIO3(_id, _name, _parent, _shift) { \
  39. .id = _id, \
  40. .name = _name, \
  41. .parent_name = _parent, \
  42. .regs = &audio3_cg_regs, \
  43. .shift = _shift, \
  44. .ops = &mtk_clk_gate_ops_no_setclr, \
  45. }
  46. static const struct mtk_gate_regs audio0_cg_regs = {
  47. .set_ofs = 0x0,
  48. .clr_ofs = 0x0,
  49. .sta_ofs = 0x0,
  50. };
  51. static const struct mtk_gate_regs audio1_cg_regs = {
  52. .set_ofs = 0x10,
  53. .clr_ofs = 0x10,
  54. .sta_ofs = 0x10,
  55. };
  56. static const struct mtk_gate_regs audio2_cg_regs = {
  57. .set_ofs = 0x14,
  58. .clr_ofs = 0x14,
  59. .sta_ofs = 0x14,
  60. };
  61. static const struct mtk_gate_regs audio3_cg_regs = {
  62. .set_ofs = 0x634,
  63. .clr_ofs = 0x634,
  64. .sta_ofs = 0x634,
  65. };
  66. static const struct mtk_gate audio_clks[] = {
  67. /* AUDIO0 */
  68. GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
  69. GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
  70. GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
  71. GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
  72. GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
  73. /* AUDIO1 */
  74. GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
  75. GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
  76. GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
  77. GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
  78. GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
  79. GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
  80. GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
  81. GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
  82. GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
  83. GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
  84. GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
  85. GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
  86. GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
  87. GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
  88. GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
  89. GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
  90. GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
  91. GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
  92. GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
  93. GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
  94. GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
  95. /* AUDIO2 */
  96. GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
  97. GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
  98. GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
  99. GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
  100. GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
  101. GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
  102. GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
  103. GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
  104. GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
  105. GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
  106. GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
  107. GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
  108. GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
  109. GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
  110. GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
  111. GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
  112. GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
  113. /* AUDIO3 */
  114. GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
  115. GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
  116. GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
  117. GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
  118. GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
  119. GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
  120. GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
  121. GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
  122. GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
  123. GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
  124. GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
  125. GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
  126. GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
  127. };
  128. static const struct of_device_id of_match_clk_mt2701_aud[] = {
  129. { .compatible = "mediatek,mt2701-audsys", },
  130. {}
  131. };
  132. static int clk_mt2701_aud_probe(struct platform_device *pdev)
  133. {
  134. struct clk_onecell_data *clk_data;
  135. struct device_node *node = pdev->dev.of_node;
  136. int r;
  137. clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
  138. mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
  139. clk_data);
  140. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  141. if (r) {
  142. dev_err(&pdev->dev,
  143. "could not register clock provider: %s: %d\n",
  144. pdev->name, r);
  145. goto err_clk_provider;
  146. }
  147. r = devm_of_platform_populate(&pdev->dev);
  148. if (r)
  149. goto err_plat_populate;
  150. return 0;
  151. err_plat_populate:
  152. of_clk_del_provider(node);
  153. err_clk_provider:
  154. return r;
  155. }
  156. static struct platform_driver clk_mt2701_aud_drv = {
  157. .probe = clk_mt2701_aud_probe,
  158. .driver = {
  159. .name = "clk-mt2701-aud",
  160. .of_match_table = of_match_clk_mt2701_aud,
  161. },
  162. };
  163. builtin_platform_driver(clk_mt2701_aud_drv);