x1000-cgu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * X1000 SoC CGU driver
  4. * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/of.h>
  10. #include <dt-bindings/clock/x1000-cgu.h>
  11. #include "cgu.h"
  12. #include "pm.h"
  13. /* CGU register offsets */
  14. #define CGU_REG_CPCCR 0x00
  15. #define CGU_REG_APLL 0x10
  16. #define CGU_REG_MPLL 0x14
  17. #define CGU_REG_CLKGR 0x20
  18. #define CGU_REG_OPCR 0x24
  19. #define CGU_REG_DDRCDR 0x2c
  20. #define CGU_REG_USBPCR 0x3c
  21. #define CGU_REG_USBPCR1 0x48
  22. #define CGU_REG_USBCDR 0x50
  23. #define CGU_REG_MACCDR 0x54
  24. #define CGU_REG_I2SCDR 0x60
  25. #define CGU_REG_LPCDR 0x64
  26. #define CGU_REG_MSC0CDR 0x68
  27. #define CGU_REG_I2SCDR1 0x70
  28. #define CGU_REG_SSICDR 0x74
  29. #define CGU_REG_CIMCDR 0x7c
  30. #define CGU_REG_PCMCDR 0x84
  31. #define CGU_REG_MSC1CDR 0xa4
  32. #define CGU_REG_CMP_INTR 0xb0
  33. #define CGU_REG_CMP_INTRE 0xb4
  34. #define CGU_REG_DRCG 0xd0
  35. #define CGU_REG_CPCSR 0xd4
  36. #define CGU_REG_PCMCDR1 0xe0
  37. #define CGU_REG_MACPHYC 0xe8
  38. /* bits within the OPCR register */
  39. #define OPCR_SPENDN0 BIT(7)
  40. #define OPCR_SPENDN1 BIT(6)
  41. /* bits within the USBPCR register */
  42. #define USBPCR_SIDDQ BIT(21)
  43. #define USBPCR_OTG_DISABLE BIT(20)
  44. /* bits within the USBPCR1 register */
  45. #define USBPCR1_REFCLKSEL_SHIFT 26
  46. #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
  47. #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
  48. #define USBPCR1_REFCLKDIV_SHIFT 24
  49. #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
  50. #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
  51. #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
  52. #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
  53. static struct ingenic_cgu *cgu;
  54. static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
  55. unsigned long parent_rate)
  56. {
  57. u32 usbpcr1;
  58. unsigned refclk_div;
  59. usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
  60. refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
  61. switch (refclk_div) {
  62. case USBPCR1_REFCLKDIV_12:
  63. return 12000000;
  64. case USBPCR1_REFCLKDIV_24:
  65. return 24000000;
  66. case USBPCR1_REFCLKDIV_48:
  67. return 48000000;
  68. }
  69. return parent_rate;
  70. }
  71. static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
  72. unsigned long *parent_rate)
  73. {
  74. if (req_rate < 18000000)
  75. return 12000000;
  76. if (req_rate < 36000000)
  77. return 24000000;
  78. return 48000000;
  79. }
  80. static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
  81. unsigned long parent_rate)
  82. {
  83. unsigned long flags;
  84. u32 usbpcr1, div_bits;
  85. switch (req_rate) {
  86. case 12000000:
  87. div_bits = USBPCR1_REFCLKDIV_12;
  88. break;
  89. case 24000000:
  90. div_bits = USBPCR1_REFCLKDIV_24;
  91. break;
  92. case 48000000:
  93. div_bits = USBPCR1_REFCLKDIV_48;
  94. break;
  95. default:
  96. return -EINVAL;
  97. }
  98. spin_lock_irqsave(&cgu->lock, flags);
  99. usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
  100. usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
  101. usbpcr1 |= div_bits;
  102. writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
  103. spin_unlock_irqrestore(&cgu->lock, flags);
  104. return 0;
  105. }
  106. static int x1000_usb_phy_enable(struct clk_hw *hw)
  107. {
  108. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  109. void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
  110. writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
  111. writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
  112. return 0;
  113. }
  114. static void x1000_usb_phy_disable(struct clk_hw *hw)
  115. {
  116. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  117. void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
  118. writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
  119. writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
  120. }
  121. static int x1000_usb_phy_is_enabled(struct clk_hw *hw)
  122. {
  123. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  124. void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
  125. return (readl(reg_opcr) & OPCR_SPENDN0) &&
  126. !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
  127. !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
  128. }
  129. static const struct clk_ops x1000_otg_phy_ops = {
  130. .recalc_rate = x1000_otg_phy_recalc_rate,
  131. .round_rate = x1000_otg_phy_round_rate,
  132. .set_rate = x1000_otg_phy_set_rate,
  133. .enable = x1000_usb_phy_enable,
  134. .disable = x1000_usb_phy_disable,
  135. .is_enabled = x1000_usb_phy_is_enabled,
  136. };
  137. static const s8 pll_od_encoding[8] = {
  138. 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
  139. };
  140. static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
  141. /* External clocks */
  142. [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
  143. [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
  144. /* PLLs */
  145. [X1000_CLK_APLL] = {
  146. "apll", CGU_CLK_PLL,
  147. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  148. .pll = {
  149. .reg = CGU_REG_APLL,
  150. .rate_multiplier = 1,
  151. .m_shift = 24,
  152. .m_bits = 7,
  153. .m_offset = 1,
  154. .n_shift = 18,
  155. .n_bits = 5,
  156. .n_offset = 1,
  157. .od_shift = 16,
  158. .od_bits = 2,
  159. .od_max = 8,
  160. .od_encoding = pll_od_encoding,
  161. .bypass_reg = CGU_REG_APLL,
  162. .bypass_bit = 9,
  163. .enable_bit = 8,
  164. .stable_bit = 10,
  165. },
  166. },
  167. [X1000_CLK_MPLL] = {
  168. "mpll", CGU_CLK_PLL,
  169. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  170. .pll = {
  171. .reg = CGU_REG_MPLL,
  172. .rate_multiplier = 1,
  173. .m_shift = 24,
  174. .m_bits = 7,
  175. .m_offset = 1,
  176. .n_shift = 18,
  177. .n_bits = 5,
  178. .n_offset = 1,
  179. .od_shift = 16,
  180. .od_bits = 2,
  181. .od_max = 8,
  182. .od_encoding = pll_od_encoding,
  183. .bypass_reg = CGU_REG_MPLL,
  184. .bypass_bit = 6,
  185. .enable_bit = 7,
  186. .stable_bit = 0,
  187. },
  188. },
  189. /* Custom (SoC-specific) OTG PHY */
  190. [X1000_CLK_OTGPHY] = {
  191. "otg_phy", CGU_CLK_CUSTOM,
  192. .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
  193. .custom = { &x1000_otg_phy_ops },
  194. },
  195. /* Muxes & dividers */
  196. [X1000_CLK_SCLKA] = {
  197. "sclk_a", CGU_CLK_MUX,
  198. .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
  199. .mux = { CGU_REG_CPCCR, 30, 2 },
  200. },
  201. [X1000_CLK_CPUMUX] = {
  202. "cpu_mux", CGU_CLK_MUX,
  203. .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
  204. .mux = { CGU_REG_CPCCR, 28, 2 },
  205. },
  206. [X1000_CLK_CPU] = {
  207. "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
  208. .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
  209. .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
  210. .gate = { CGU_REG_CLKGR, 30 },
  211. },
  212. [X1000_CLK_L2CACHE] = {
  213. "l2cache", CGU_CLK_DIV,
  214. .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
  215. .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
  216. },
  217. [X1000_CLK_AHB0] = {
  218. "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
  219. .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
  220. .mux = { CGU_REG_CPCCR, 26, 2 },
  221. .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
  222. },
  223. [X1000_CLK_AHB2PMUX] = {
  224. "ahb2_apb_mux", CGU_CLK_MUX,
  225. .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
  226. .mux = { CGU_REG_CPCCR, 24, 2 },
  227. },
  228. [X1000_CLK_AHB2] = {
  229. "ahb2", CGU_CLK_DIV,
  230. .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
  231. .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
  232. },
  233. [X1000_CLK_PCLK] = {
  234. "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
  235. .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
  236. .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
  237. .gate = { CGU_REG_CLKGR, 28 },
  238. },
  239. [X1000_CLK_DDR] = {
  240. "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  241. .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
  242. .mux = { CGU_REG_DDRCDR, 30, 2 },
  243. .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
  244. .gate = { CGU_REG_CLKGR, 31 },
  245. },
  246. [X1000_CLK_MAC] = {
  247. "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  248. .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
  249. .mux = { CGU_REG_MACCDR, 31, 1 },
  250. .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
  251. .gate = { CGU_REG_CLKGR, 25 },
  252. },
  253. [X1000_CLK_LCD] = {
  254. "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  255. .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
  256. .mux = { CGU_REG_LPCDR, 31, 1 },
  257. .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
  258. .gate = { CGU_REG_CLKGR, 23 },
  259. },
  260. [X1000_CLK_MSCMUX] = {
  261. "msc_mux", CGU_CLK_MUX,
  262. .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
  263. .mux = { CGU_REG_MSC0CDR, 31, 1 },
  264. },
  265. [X1000_CLK_MSC0] = {
  266. "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
  267. .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
  268. .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
  269. .gate = { CGU_REG_CLKGR, 4 },
  270. },
  271. [X1000_CLK_MSC1] = {
  272. "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
  273. .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
  274. .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
  275. .gate = { CGU_REG_CLKGR, 5 },
  276. },
  277. [X1000_CLK_OTG] = {
  278. "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  279. .parents = { X1000_CLK_EXCLK, -1,
  280. X1000_CLK_APLL, X1000_CLK_MPLL },
  281. .mux = { CGU_REG_USBCDR, 30, 2 },
  282. .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 },
  283. .gate = { CGU_REG_CLKGR, 3 },
  284. },
  285. [X1000_CLK_SSIPLL] = {
  286. "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
  287. .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
  288. .mux = { CGU_REG_SSICDR, 31, 1 },
  289. .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
  290. },
  291. [X1000_CLK_SSIPLL_DIV2] = {
  292. "ssi_pll_div2", CGU_CLK_FIXDIV,
  293. .parents = { X1000_CLK_SSIPLL },
  294. .fixdiv = { 2 },
  295. },
  296. [X1000_CLK_SSIMUX] = {
  297. "ssi_mux", CGU_CLK_MUX,
  298. .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
  299. .mux = { CGU_REG_SSICDR, 30, 1 },
  300. },
  301. [X1000_CLK_EXCLK_DIV512] = {
  302. "exclk_div512", CGU_CLK_FIXDIV,
  303. .parents = { X1000_CLK_EXCLK },
  304. .fixdiv = { 512 },
  305. },
  306. [X1000_CLK_RTC] = {
  307. "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
  308. .parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
  309. .mux = { CGU_REG_OPCR, 2, 1},
  310. .gate = { CGU_REG_CLKGR, 27 },
  311. },
  312. /* Gate-only clocks */
  313. [X1000_CLK_EMC] = {
  314. "emc", CGU_CLK_GATE,
  315. .parents = { X1000_CLK_AHB2, -1, -1, -1 },
  316. .gate = { CGU_REG_CLKGR, 0 },
  317. },
  318. [X1000_CLK_EFUSE] = {
  319. "efuse", CGU_CLK_GATE,
  320. .parents = { X1000_CLK_AHB2, -1, -1, -1 },
  321. .gate = { CGU_REG_CLKGR, 1 },
  322. },
  323. [X1000_CLK_SFC] = {
  324. "sfc", CGU_CLK_GATE,
  325. .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
  326. .gate = { CGU_REG_CLKGR, 2 },
  327. },
  328. [X1000_CLK_I2C0] = {
  329. "i2c0", CGU_CLK_GATE,
  330. .parents = { X1000_CLK_PCLK, -1, -1, -1 },
  331. .gate = { CGU_REG_CLKGR, 7 },
  332. },
  333. [X1000_CLK_I2C1] = {
  334. "i2c1", CGU_CLK_GATE,
  335. .parents = { X1000_CLK_PCLK, -1, -1, -1 },
  336. .gate = { CGU_REG_CLKGR, 8 },
  337. },
  338. [X1000_CLK_I2C2] = {
  339. "i2c2", CGU_CLK_GATE,
  340. .parents = { X1000_CLK_PCLK, -1, -1, -1 },
  341. .gate = { CGU_REG_CLKGR, 9 },
  342. },
  343. [X1000_CLK_UART0] = {
  344. "uart0", CGU_CLK_GATE,
  345. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  346. .gate = { CGU_REG_CLKGR, 14 },
  347. },
  348. [X1000_CLK_UART1] = {
  349. "uart1", CGU_CLK_GATE,
  350. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  351. .gate = { CGU_REG_CLKGR, 15 },
  352. },
  353. [X1000_CLK_UART2] = {
  354. "uart2", CGU_CLK_GATE,
  355. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  356. .gate = { CGU_REG_CLKGR, 16 },
  357. },
  358. [X1000_CLK_TCU] = {
  359. "tcu", CGU_CLK_GATE,
  360. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  361. .gate = { CGU_REG_CLKGR, 18 },
  362. },
  363. [X1000_CLK_SSI] = {
  364. "ssi", CGU_CLK_GATE,
  365. .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
  366. .gate = { CGU_REG_CLKGR, 19 },
  367. },
  368. [X1000_CLK_OST] = {
  369. "ost", CGU_CLK_GATE,
  370. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  371. .gate = { CGU_REG_CLKGR, 20 },
  372. },
  373. [X1000_CLK_PDMA] = {
  374. "pdma", CGU_CLK_GATE,
  375. .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
  376. .gate = { CGU_REG_CLKGR, 21 },
  377. },
  378. };
  379. static void __init x1000_cgu_init(struct device_node *np)
  380. {
  381. int retval;
  382. cgu = ingenic_cgu_new(x1000_cgu_clocks,
  383. ARRAY_SIZE(x1000_cgu_clocks), np);
  384. if (!cgu) {
  385. pr_err("%s: failed to initialise CGU\n", __func__);
  386. return;
  387. }
  388. retval = ingenic_cgu_register_clocks(cgu);
  389. if (retval) {
  390. pr_err("%s: failed to register CGU Clocks\n", __func__);
  391. return;
  392. }
  393. ingenic_cgu_register_syscore_ops(cgu);
  394. }
  395. /*
  396. * CGU has some children devices, this is useful for probing children devices
  397. * in the case where the device node is compatible with "simple-mfd".
  398. */
  399. CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);