tcu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * JZ47xx SoCs TCU clocks driver
  4. * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/clockchips.h>
  9. #include <linux/mfd/ingenic-tcu.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <linux/syscore_ops.h>
  14. #include <dt-bindings/clock/ingenic,tcu.h>
  15. /* 8 channels max + watchdog + OST */
  16. #define TCU_CLK_COUNT 10
  17. #undef pr_fmt
  18. #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
  19. enum tcu_clk_parent {
  20. TCU_PARENT_PCLK,
  21. TCU_PARENT_RTC,
  22. TCU_PARENT_EXT,
  23. };
  24. struct ingenic_soc_info {
  25. unsigned int num_channels;
  26. bool has_ost;
  27. bool has_tcu_clk;
  28. };
  29. struct ingenic_tcu_clk_info {
  30. struct clk_init_data init_data;
  31. u8 gate_bit;
  32. u8 tcsr_reg;
  33. };
  34. struct ingenic_tcu_clk {
  35. struct clk_hw hw;
  36. unsigned int idx;
  37. struct ingenic_tcu *tcu;
  38. const struct ingenic_tcu_clk_info *info;
  39. };
  40. struct ingenic_tcu {
  41. const struct ingenic_soc_info *soc_info;
  42. struct regmap *map;
  43. struct clk *clk;
  44. struct clk_hw_onecell_data *clocks;
  45. };
  46. static struct ingenic_tcu *ingenic_tcu;
  47. static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
  48. {
  49. return container_of(hw, struct ingenic_tcu_clk, hw);
  50. }
  51. static int ingenic_tcu_enable(struct clk_hw *hw)
  52. {
  53. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  54. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  55. struct ingenic_tcu *tcu = tcu_clk->tcu;
  56. regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
  57. return 0;
  58. }
  59. static void ingenic_tcu_disable(struct clk_hw *hw)
  60. {
  61. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  62. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  63. struct ingenic_tcu *tcu = tcu_clk->tcu;
  64. regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
  65. }
  66. static int ingenic_tcu_is_enabled(struct clk_hw *hw)
  67. {
  68. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  69. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  70. unsigned int value;
  71. regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
  72. return !(value & BIT(info->gate_bit));
  73. }
  74. static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
  75. {
  76. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  77. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  78. struct ingenic_tcu *tcu = tcu_clk->tcu;
  79. bool enabled = false;
  80. /*
  81. * If the SoC has no global TCU clock, we must ungate the channel's
  82. * clock to be able to access its registers.
  83. * If we have a TCU clock, it will be enabled automatically as it has
  84. * been attached to the regmap.
  85. */
  86. if (!tcu->clk) {
  87. enabled = !!ingenic_tcu_is_enabled(hw);
  88. regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
  89. }
  90. return enabled;
  91. }
  92. static void ingenic_tcu_disable_regs(struct clk_hw *hw)
  93. {
  94. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  95. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  96. struct ingenic_tcu *tcu = tcu_clk->tcu;
  97. if (!tcu->clk)
  98. regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
  99. }
  100. static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
  101. {
  102. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  103. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  104. unsigned int val = 0;
  105. int ret;
  106. ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
  107. WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
  108. return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
  109. }
  110. static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
  111. {
  112. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  113. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  114. bool was_enabled;
  115. int ret;
  116. was_enabled = ingenic_tcu_enable_regs(hw);
  117. ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
  118. TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
  119. WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
  120. if (!was_enabled)
  121. ingenic_tcu_disable_regs(hw);
  122. return 0;
  123. }
  124. static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
  125. unsigned long parent_rate)
  126. {
  127. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  128. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  129. unsigned int prescale;
  130. int ret;
  131. ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
  132. WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
  133. prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
  134. return parent_rate >> (prescale * 2);
  135. }
  136. static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
  137. {
  138. u8 prescale;
  139. for (prescale = 0; prescale < 5; prescale++)
  140. if ((rate >> (prescale * 2)) <= req_rate)
  141. return prescale;
  142. return 5; /* /1024 divider */
  143. }
  144. static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
  145. unsigned long *parent_rate)
  146. {
  147. unsigned long rate = *parent_rate;
  148. u8 prescale;
  149. if (req_rate > rate)
  150. return rate;
  151. prescale = ingenic_tcu_get_prescale(rate, req_rate);
  152. return rate >> (prescale * 2);
  153. }
  154. static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
  155. unsigned long parent_rate)
  156. {
  157. struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
  158. const struct ingenic_tcu_clk_info *info = tcu_clk->info;
  159. u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
  160. bool was_enabled;
  161. int ret;
  162. was_enabled = ingenic_tcu_enable_regs(hw);
  163. ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
  164. TCU_TCSR_PRESCALE_MASK,
  165. prescale << TCU_TCSR_PRESCALE_LSB);
  166. WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
  167. if (!was_enabled)
  168. ingenic_tcu_disable_regs(hw);
  169. return 0;
  170. }
  171. static const struct clk_ops ingenic_tcu_clk_ops = {
  172. .get_parent = ingenic_tcu_get_parent,
  173. .set_parent = ingenic_tcu_set_parent,
  174. .recalc_rate = ingenic_tcu_recalc_rate,
  175. .round_rate = ingenic_tcu_round_rate,
  176. .set_rate = ingenic_tcu_set_rate,
  177. .enable = ingenic_tcu_enable,
  178. .disable = ingenic_tcu_disable,
  179. .is_enabled = ingenic_tcu_is_enabled,
  180. };
  181. static const char * const ingenic_tcu_timer_parents[] = {
  182. [TCU_PARENT_PCLK] = "pclk",
  183. [TCU_PARENT_RTC] = "rtc",
  184. [TCU_PARENT_EXT] = "ext",
  185. };
  186. #define DEF_TIMER(_name, _gate_bit, _tcsr) \
  187. { \
  188. .init_data = { \
  189. .name = _name, \
  190. .parent_names = ingenic_tcu_timer_parents, \
  191. .num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
  192. .ops = &ingenic_tcu_clk_ops, \
  193. .flags = CLK_SET_RATE_UNGATE, \
  194. }, \
  195. .gate_bit = _gate_bit, \
  196. .tcsr_reg = _tcsr, \
  197. }
  198. static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
  199. [TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
  200. [TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
  201. [TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
  202. [TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
  203. [TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
  204. [TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
  205. [TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
  206. [TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
  207. };
  208. static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
  209. DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
  210. static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
  211. DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
  212. #undef DEF_TIMER
  213. static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
  214. unsigned int idx, enum tcu_clk_parent parent,
  215. const struct ingenic_tcu_clk_info *info,
  216. struct clk_hw_onecell_data *clocks)
  217. {
  218. struct ingenic_tcu_clk *tcu_clk;
  219. int err;
  220. tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
  221. if (!tcu_clk)
  222. return -ENOMEM;
  223. tcu_clk->hw.init = &info->init_data;
  224. tcu_clk->idx = idx;
  225. tcu_clk->info = info;
  226. tcu_clk->tcu = tcu;
  227. /* Reset channel and clock divider, set default parent */
  228. ingenic_tcu_enable_regs(&tcu_clk->hw);
  229. regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
  230. ingenic_tcu_disable_regs(&tcu_clk->hw);
  231. err = clk_hw_register(NULL, &tcu_clk->hw);
  232. if (err) {
  233. kfree(tcu_clk);
  234. return err;
  235. }
  236. clocks->hws[idx] = &tcu_clk->hw;
  237. return 0;
  238. }
  239. static const struct ingenic_soc_info jz4740_soc_info = {
  240. .num_channels = 8,
  241. .has_ost = false,
  242. .has_tcu_clk = true,
  243. };
  244. static const struct ingenic_soc_info jz4725b_soc_info = {
  245. .num_channels = 6,
  246. .has_ost = true,
  247. .has_tcu_clk = true,
  248. };
  249. static const struct ingenic_soc_info jz4770_soc_info = {
  250. .num_channels = 8,
  251. .has_ost = true,
  252. .has_tcu_clk = false,
  253. };
  254. static const struct ingenic_soc_info x1000_soc_info = {
  255. .num_channels = 8,
  256. .has_ost = false, /* X1000 has OST, but it not belong TCU */
  257. .has_tcu_clk = false,
  258. };
  259. static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
  260. { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
  261. { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
  262. { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
  263. { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
  264. { /* sentinel */ }
  265. };
  266. static int __init ingenic_tcu_probe(struct device_node *np)
  267. {
  268. const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
  269. struct ingenic_tcu *tcu;
  270. struct regmap *map;
  271. unsigned int i;
  272. int ret;
  273. map = device_node_to_regmap(np);
  274. if (IS_ERR(map))
  275. return PTR_ERR(map);
  276. tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
  277. if (!tcu)
  278. return -ENOMEM;
  279. tcu->map = map;
  280. tcu->soc_info = id->data;
  281. if (tcu->soc_info->has_tcu_clk) {
  282. tcu->clk = of_clk_get_by_name(np, "tcu");
  283. if (IS_ERR(tcu->clk)) {
  284. ret = PTR_ERR(tcu->clk);
  285. pr_crit("Cannot get TCU clock\n");
  286. goto err_free_tcu;
  287. }
  288. ret = clk_prepare_enable(tcu->clk);
  289. if (ret) {
  290. pr_crit("Unable to enable TCU clock\n");
  291. goto err_put_clk;
  292. }
  293. }
  294. tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT),
  295. GFP_KERNEL);
  296. if (!tcu->clocks) {
  297. ret = -ENOMEM;
  298. goto err_clk_disable;
  299. }
  300. tcu->clocks->num = TCU_CLK_COUNT;
  301. for (i = 0; i < tcu->soc_info->num_channels; i++) {
  302. ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
  303. &ingenic_tcu_clk_info[i],
  304. tcu->clocks);
  305. if (ret) {
  306. pr_crit("cannot register clock %d\n", i);
  307. goto err_unregister_timer_clocks;
  308. }
  309. }
  310. /*
  311. * We set EXT as the default parent clock for all the TCU clocks
  312. * except for the watchdog one, where we set the RTC clock as the
  313. * parent. Since the EXT and PCLK are much faster than the RTC clock,
  314. * the watchdog would kick after a maximum time of 5s, and we might
  315. * want a slower kicking time.
  316. */
  317. ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
  318. &ingenic_tcu_watchdog_clk_info,
  319. tcu->clocks);
  320. if (ret) {
  321. pr_crit("cannot register watchdog clock\n");
  322. goto err_unregister_timer_clocks;
  323. }
  324. if (tcu->soc_info->has_ost) {
  325. ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
  326. TCU_PARENT_EXT,
  327. &ingenic_tcu_ost_clk_info,
  328. tcu->clocks);
  329. if (ret) {
  330. pr_crit("cannot register ost clock\n");
  331. goto err_unregister_watchdog_clock;
  332. }
  333. }
  334. ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
  335. if (ret) {
  336. pr_crit("cannot add OF clock provider\n");
  337. goto err_unregister_ost_clock;
  338. }
  339. ingenic_tcu = tcu;
  340. return 0;
  341. err_unregister_ost_clock:
  342. if (tcu->soc_info->has_ost)
  343. clk_hw_unregister(tcu->clocks->hws[i + 1]);
  344. err_unregister_watchdog_clock:
  345. clk_hw_unregister(tcu->clocks->hws[i]);
  346. err_unregister_timer_clocks:
  347. for (i = 0; i < tcu->clocks->num; i++)
  348. if (tcu->clocks->hws[i])
  349. clk_hw_unregister(tcu->clocks->hws[i]);
  350. kfree(tcu->clocks);
  351. err_clk_disable:
  352. if (tcu->soc_info->has_tcu_clk)
  353. clk_disable_unprepare(tcu->clk);
  354. err_put_clk:
  355. if (tcu->soc_info->has_tcu_clk)
  356. clk_put(tcu->clk);
  357. err_free_tcu:
  358. kfree(tcu);
  359. return ret;
  360. }
  361. static int __maybe_unused tcu_pm_suspend(void)
  362. {
  363. struct ingenic_tcu *tcu = ingenic_tcu;
  364. if (tcu->clk)
  365. clk_disable(tcu->clk);
  366. return 0;
  367. }
  368. static void __maybe_unused tcu_pm_resume(void)
  369. {
  370. struct ingenic_tcu *tcu = ingenic_tcu;
  371. if (tcu->clk)
  372. clk_enable(tcu->clk);
  373. }
  374. static struct syscore_ops __maybe_unused tcu_pm_ops = {
  375. .suspend = tcu_pm_suspend,
  376. .resume = tcu_pm_resume,
  377. };
  378. static void __init ingenic_tcu_init(struct device_node *np)
  379. {
  380. int ret = ingenic_tcu_probe(np);
  381. if (ret)
  382. pr_crit("Failed to initialize TCU clocks: %d\n", ret);
  383. if (IS_ENABLED(CONFIG_PM_SLEEP))
  384. register_syscore_ops(&tcu_pm_ops);
  385. }
  386. CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
  387. CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
  388. CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
  389. CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);