jz4780-cgu.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Ingenic JZ4780 SoC CGU driver
  4. *
  5. * Copyright (c) 2013-2015 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@mips.com>
  7. * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/of.h>
  14. #include <dt-bindings/clock/jz4780-cgu.h>
  15. #include "cgu.h"
  16. #include "pm.h"
  17. /* CGU register offsets */
  18. #define CGU_REG_CLOCKCONTROL 0x00
  19. #define CGU_REG_LCR 0x04
  20. #define CGU_REG_APLL 0x10
  21. #define CGU_REG_MPLL 0x14
  22. #define CGU_REG_EPLL 0x18
  23. #define CGU_REG_VPLL 0x1c
  24. #define CGU_REG_CLKGR0 0x20
  25. #define CGU_REG_OPCR 0x24
  26. #define CGU_REG_CLKGR1 0x28
  27. #define CGU_REG_DDRCDR 0x2c
  28. #define CGU_REG_VPUCDR 0x30
  29. #define CGU_REG_USBPCR 0x3c
  30. #define CGU_REG_USBRDT 0x40
  31. #define CGU_REG_USBVBFIL 0x44
  32. #define CGU_REG_USBPCR1 0x48
  33. #define CGU_REG_LP0CDR 0x54
  34. #define CGU_REG_I2SCDR 0x60
  35. #define CGU_REG_LP1CDR 0x64
  36. #define CGU_REG_MSC0CDR 0x68
  37. #define CGU_REG_UHCCDR 0x6c
  38. #define CGU_REG_SSICDR 0x74
  39. #define CGU_REG_CIMCDR 0x7c
  40. #define CGU_REG_PCMCDR 0x84
  41. #define CGU_REG_GPUCDR 0x88
  42. #define CGU_REG_HDMICDR 0x8c
  43. #define CGU_REG_MSC1CDR 0xa4
  44. #define CGU_REG_MSC2CDR 0xa8
  45. #define CGU_REG_BCHCDR 0xac
  46. #define CGU_REG_CLOCKSTATUS 0xd4
  47. /* bits within the OPCR register */
  48. #define OPCR_SPENDN0 BIT(7)
  49. #define OPCR_SPENDN1 BIT(6)
  50. /* bits within the USBPCR register */
  51. #define USBPCR_USB_MODE BIT(31)
  52. #define USBPCR_IDPULLUP_MASK (0x3 << 28)
  53. #define USBPCR_COMMONONN BIT(25)
  54. #define USBPCR_VBUSVLDEXT BIT(24)
  55. #define USBPCR_VBUSVLDEXTSEL BIT(23)
  56. #define USBPCR_POR BIT(22)
  57. #define USBPCR_SIDDQ BIT(21)
  58. #define USBPCR_OTG_DISABLE BIT(20)
  59. #define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
  60. #define USBPCR_OTGTUNE_MASK (0x7 << 14)
  61. #define USBPCR_SQRXTUNE_MASK (0x7 << 11)
  62. #define USBPCR_TXFSLSTUNE_MASK (0xf << 7)
  63. #define USBPCR_TXPREEMPHTUNE BIT(6)
  64. #define USBPCR_TXHSXVTUNE_MASK (0x3 << 4)
  65. #define USBPCR_TXVREFTUNE_MASK 0xf
  66. /* bits within the USBPCR1 register */
  67. #define USBPCR1_REFCLKSEL_SHIFT 26
  68. #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
  69. #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
  70. #define USBPCR1_REFCLKDIV_SHIFT 24
  71. #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
  72. #define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT)
  73. #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
  74. #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
  75. #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
  76. #define USBPCR1_USB_SEL BIT(28)
  77. #define USBPCR1_WORD_IF0 BIT(19)
  78. #define USBPCR1_WORD_IF1 BIT(18)
  79. /* bits within the USBRDT register */
  80. #define USBRDT_VBFIL_LD_EN BIT(25)
  81. #define USBRDT_USBRDT_MASK 0x7fffff
  82. /* bits within the USBVBFIL register */
  83. #define USBVBFIL_IDDIGFIL_SHIFT 16
  84. #define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT)
  85. #define USBVBFIL_USBVBFIL_MASK (0xffff)
  86. /* bits within the LCR register */
  87. #define LCR_PD_SCPU BIT(31)
  88. #define LCR_SCPUS BIT(27)
  89. /* bits within the CLKGR1 register */
  90. #define CLKGR1_CORE1 BIT(15)
  91. static struct ingenic_cgu *cgu;
  92. static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
  93. unsigned long parent_rate)
  94. {
  95. u32 usbpcr1;
  96. unsigned refclk_div;
  97. usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
  98. refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
  99. switch (refclk_div) {
  100. case USBPCR1_REFCLKDIV_12:
  101. return 12000000;
  102. case USBPCR1_REFCLKDIV_24:
  103. return 24000000;
  104. case USBPCR1_REFCLKDIV_48:
  105. return 48000000;
  106. case USBPCR1_REFCLKDIV_19_2:
  107. return 19200000;
  108. }
  109. return parent_rate;
  110. }
  111. static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
  112. unsigned long *parent_rate)
  113. {
  114. if (req_rate < 15600000)
  115. return 12000000;
  116. if (req_rate < 21600000)
  117. return 19200000;
  118. if (req_rate < 36000000)
  119. return 24000000;
  120. return 48000000;
  121. }
  122. static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
  123. unsigned long parent_rate)
  124. {
  125. unsigned long flags;
  126. u32 usbpcr1, div_bits;
  127. switch (req_rate) {
  128. case 12000000:
  129. div_bits = USBPCR1_REFCLKDIV_12;
  130. break;
  131. case 19200000:
  132. div_bits = USBPCR1_REFCLKDIV_19_2;
  133. break;
  134. case 24000000:
  135. div_bits = USBPCR1_REFCLKDIV_24;
  136. break;
  137. case 48000000:
  138. div_bits = USBPCR1_REFCLKDIV_48;
  139. break;
  140. default:
  141. return -EINVAL;
  142. }
  143. spin_lock_irqsave(&cgu->lock, flags);
  144. usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
  145. usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
  146. usbpcr1 |= div_bits;
  147. writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
  148. spin_unlock_irqrestore(&cgu->lock, flags);
  149. return 0;
  150. }
  151. static int jz4780_otg_phy_enable(struct clk_hw *hw)
  152. {
  153. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  154. void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
  155. writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
  156. writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
  157. return 0;
  158. }
  159. static void jz4780_otg_phy_disable(struct clk_hw *hw)
  160. {
  161. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  162. void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
  163. writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
  164. writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
  165. }
  166. static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
  167. {
  168. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  169. void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
  170. return (readl(reg_opcr) & OPCR_SPENDN0) &&
  171. !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
  172. !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
  173. }
  174. static const struct clk_ops jz4780_otg_phy_ops = {
  175. .recalc_rate = jz4780_otg_phy_recalc_rate,
  176. .round_rate = jz4780_otg_phy_round_rate,
  177. .set_rate = jz4780_otg_phy_set_rate,
  178. .enable = jz4780_otg_phy_enable,
  179. .disable = jz4780_otg_phy_disable,
  180. .is_enabled = jz4780_otg_phy_is_enabled,
  181. };
  182. static int jz4780_core1_enable(struct clk_hw *hw)
  183. {
  184. struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
  185. struct ingenic_cgu *cgu = ingenic_clk->cgu;
  186. const unsigned int timeout = 5000;
  187. unsigned long flags;
  188. int retval;
  189. u32 lcr, clkgr1;
  190. spin_lock_irqsave(&cgu->lock, flags);
  191. lcr = readl(cgu->base + CGU_REG_LCR);
  192. lcr &= ~LCR_PD_SCPU;
  193. writel(lcr, cgu->base + CGU_REG_LCR);
  194. clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
  195. clkgr1 &= ~CLKGR1_CORE1;
  196. writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
  197. spin_unlock_irqrestore(&cgu->lock, flags);
  198. /* wait for the CPU to be powered up */
  199. retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr,
  200. !(lcr & LCR_SCPUS), 10, timeout);
  201. if (retval == -ETIMEDOUT) {
  202. pr_err("%s: Wait for power up core1 timeout\n", __func__);
  203. return retval;
  204. }
  205. return 0;
  206. }
  207. static const struct clk_ops jz4780_core1_ops = {
  208. .enable = jz4780_core1_enable,
  209. };
  210. static const s8 pll_od_encoding[16] = {
  211. 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
  212. 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
  213. };
  214. static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
  215. /* External clocks */
  216. [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
  217. [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
  218. /* PLLs */
  219. #define DEF_PLL(name) { \
  220. .reg = CGU_REG_ ## name, \
  221. .rate_multiplier = 1, \
  222. .m_shift = 19, \
  223. .m_bits = 13, \
  224. .m_offset = 1, \
  225. .n_shift = 13, \
  226. .n_bits = 6, \
  227. .n_offset = 1, \
  228. .od_shift = 9, \
  229. .od_bits = 4, \
  230. .od_max = 16, \
  231. .od_encoding = pll_od_encoding, \
  232. .stable_bit = 6, \
  233. .bypass_reg = CGU_REG_ ## name, \
  234. .bypass_bit = 1, \
  235. .enable_bit = 0, \
  236. }
  237. [JZ4780_CLK_APLL] = {
  238. "apll", CGU_CLK_PLL,
  239. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  240. .pll = DEF_PLL(APLL),
  241. },
  242. [JZ4780_CLK_MPLL] = {
  243. "mpll", CGU_CLK_PLL,
  244. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  245. .pll = DEF_PLL(MPLL),
  246. },
  247. [JZ4780_CLK_EPLL] = {
  248. "epll", CGU_CLK_PLL,
  249. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  250. .pll = DEF_PLL(EPLL),
  251. },
  252. [JZ4780_CLK_VPLL] = {
  253. "vpll", CGU_CLK_PLL,
  254. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  255. .pll = DEF_PLL(VPLL),
  256. },
  257. #undef DEF_PLL
  258. /* Custom (SoC-specific) OTG PHY */
  259. [JZ4780_CLK_OTGPHY] = {
  260. "otg_phy", CGU_CLK_CUSTOM,
  261. .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
  262. .custom = { &jz4780_otg_phy_ops },
  263. },
  264. /* Muxes & dividers */
  265. [JZ4780_CLK_SCLKA] = {
  266. "sclk_a", CGU_CLK_MUX,
  267. .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
  268. JZ4780_CLK_RTCLK },
  269. .mux = { CGU_REG_CLOCKCONTROL, 30, 2 },
  270. },
  271. [JZ4780_CLK_CPUMUX] = {
  272. "cpumux", CGU_CLK_MUX,
  273. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  274. JZ4780_CLK_EPLL },
  275. .mux = { CGU_REG_CLOCKCONTROL, 28, 2 },
  276. },
  277. [JZ4780_CLK_CPU] = {
  278. "cpu", CGU_CLK_DIV,
  279. .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
  280. .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
  281. },
  282. [JZ4780_CLK_L2CACHE] = {
  283. "l2cache", CGU_CLK_DIV,
  284. .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
  285. .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
  286. },
  287. [JZ4780_CLK_AHB0] = {
  288. "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
  289. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  290. JZ4780_CLK_EPLL },
  291. .mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
  292. .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
  293. },
  294. [JZ4780_CLK_AHB2PMUX] = {
  295. "ahb2_apb_mux", CGU_CLK_MUX,
  296. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  297. JZ4780_CLK_RTCLK },
  298. .mux = { CGU_REG_CLOCKCONTROL, 24, 2 },
  299. },
  300. [JZ4780_CLK_AHB2] = {
  301. "ahb2", CGU_CLK_DIV,
  302. .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
  303. .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
  304. },
  305. [JZ4780_CLK_PCLK] = {
  306. "pclk", CGU_CLK_DIV,
  307. .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
  308. .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
  309. },
  310. [JZ4780_CLK_DDR] = {
  311. "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
  312. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
  313. .mux = { CGU_REG_DDRCDR, 30, 2 },
  314. .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
  315. },
  316. [JZ4780_CLK_VPU] = {
  317. "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  318. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  319. JZ4780_CLK_EPLL, -1 },
  320. .mux = { CGU_REG_VPUCDR, 30, 2 },
  321. .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 },
  322. .gate = { CGU_REG_CLKGR1, 2 },
  323. },
  324. [JZ4780_CLK_I2SPLL] = {
  325. "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
  326. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
  327. .mux = { CGU_REG_I2SCDR, 30, 1 },
  328. .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 },
  329. },
  330. [JZ4780_CLK_I2S] = {
  331. "i2s", CGU_CLK_MUX,
  332. .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },
  333. .mux = { CGU_REG_I2SCDR, 31, 1 },
  334. },
  335. [JZ4780_CLK_LCD0PIXCLK] = {
  336. "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
  337. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  338. JZ4780_CLK_VPLL, -1 },
  339. .mux = { CGU_REG_LP0CDR, 30, 2 },
  340. .div = { CGU_REG_LP0CDR, 0, 1, 8, 28, 27, 26 },
  341. },
  342. [JZ4780_CLK_LCD1PIXCLK] = {
  343. "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
  344. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  345. JZ4780_CLK_VPLL, -1 },
  346. .mux = { CGU_REG_LP1CDR, 30, 2 },
  347. .div = { CGU_REG_LP1CDR, 0, 1, 8, 28, 27, 26 },
  348. },
  349. [JZ4780_CLK_MSCMUX] = {
  350. "msc_mux", CGU_CLK_MUX,
  351. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
  352. .mux = { CGU_REG_MSC0CDR, 30, 2 },
  353. },
  354. [JZ4780_CLK_MSC0] = {
  355. "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
  356. .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
  357. .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
  358. .gate = { CGU_REG_CLKGR0, 3 },
  359. },
  360. [JZ4780_CLK_MSC1] = {
  361. "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
  362. .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
  363. .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
  364. .gate = { CGU_REG_CLKGR0, 11 },
  365. },
  366. [JZ4780_CLK_MSC2] = {
  367. "msc2", CGU_CLK_DIV | CGU_CLK_GATE,
  368. .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
  369. .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 },
  370. .gate = { CGU_REG_CLKGR0, 12 },
  371. },
  372. [JZ4780_CLK_UHC] = {
  373. "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  374. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  375. JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },
  376. .mux = { CGU_REG_UHCCDR, 30, 2 },
  377. .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 },
  378. .gate = { CGU_REG_CLKGR0, 24 },
  379. },
  380. [JZ4780_CLK_SSIPLL] = {
  381. "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
  382. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
  383. .mux = { CGU_REG_SSICDR, 30, 1 },
  384. .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
  385. },
  386. [JZ4780_CLK_SSI] = {
  387. "ssi", CGU_CLK_MUX,
  388. .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },
  389. .mux = { CGU_REG_SSICDR, 31, 1 },
  390. },
  391. [JZ4780_CLK_CIMMCLK] = {
  392. "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
  393. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
  394. .mux = { CGU_REG_CIMCDR, 31, 1 },
  395. .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 },
  396. },
  397. [JZ4780_CLK_PCMPLL] = {
  398. "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
  399. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  400. JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },
  401. .mux = { CGU_REG_PCMCDR, 29, 2 },
  402. .div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 },
  403. },
  404. [JZ4780_CLK_PCM] = {
  405. "pcm", CGU_CLK_MUX | CGU_CLK_GATE,
  406. .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },
  407. .mux = { CGU_REG_PCMCDR, 31, 1 },
  408. .gate = { CGU_REG_CLKGR1, 3 },
  409. },
  410. [JZ4780_CLK_GPU] = {
  411. "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  412. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  413. JZ4780_CLK_EPLL },
  414. .mux = { CGU_REG_GPUCDR, 30, 2 },
  415. .div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 },
  416. .gate = { CGU_REG_CLKGR1, 4 },
  417. },
  418. [JZ4780_CLK_HDMI] = {
  419. "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  420. .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  421. JZ4780_CLK_VPLL, -1 },
  422. .mux = { CGU_REG_HDMICDR, 30, 2 },
  423. .div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 },
  424. .gate = { CGU_REG_CLKGR1, 9 },
  425. },
  426. [JZ4780_CLK_BCH] = {
  427. "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  428. .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
  429. JZ4780_CLK_EPLL },
  430. .mux = { CGU_REG_BCHCDR, 30, 2 },
  431. .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 },
  432. .gate = { CGU_REG_CLKGR0, 1 },
  433. },
  434. [JZ4780_CLK_EXCLK_DIV512] = {
  435. "exclk_div512", CGU_CLK_FIXDIV,
  436. .parents = { JZ4780_CLK_EXCLK },
  437. .fixdiv = { 512 },
  438. },
  439. [JZ4780_CLK_RTC] = {
  440. "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
  441. .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
  442. .mux = { CGU_REG_OPCR, 2, 1},
  443. },
  444. /* Gate-only clocks */
  445. [JZ4780_CLK_NEMC] = {
  446. "nemc", CGU_CLK_GATE,
  447. .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
  448. .gate = { CGU_REG_CLKGR0, 0 },
  449. },
  450. [JZ4780_CLK_OTG0] = {
  451. "otg0", CGU_CLK_GATE,
  452. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  453. .gate = { CGU_REG_CLKGR0, 2 },
  454. },
  455. [JZ4780_CLK_SSI0] = {
  456. "ssi0", CGU_CLK_GATE,
  457. .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
  458. .gate = { CGU_REG_CLKGR0, 4 },
  459. },
  460. [JZ4780_CLK_SMB0] = {
  461. "smb0", CGU_CLK_GATE,
  462. .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
  463. .gate = { CGU_REG_CLKGR0, 5 },
  464. },
  465. [JZ4780_CLK_SMB1] = {
  466. "smb1", CGU_CLK_GATE,
  467. .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
  468. .gate = { CGU_REG_CLKGR0, 6 },
  469. },
  470. [JZ4780_CLK_SCC] = {
  471. "scc", CGU_CLK_GATE,
  472. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  473. .gate = { CGU_REG_CLKGR0, 7 },
  474. },
  475. [JZ4780_CLK_AIC] = {
  476. "aic", CGU_CLK_GATE,
  477. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  478. .gate = { CGU_REG_CLKGR0, 8 },
  479. },
  480. [JZ4780_CLK_TSSI0] = {
  481. "tssi0", CGU_CLK_GATE,
  482. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  483. .gate = { CGU_REG_CLKGR0, 9 },
  484. },
  485. [JZ4780_CLK_OWI] = {
  486. "owi", CGU_CLK_GATE,
  487. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  488. .gate = { CGU_REG_CLKGR0, 10 },
  489. },
  490. [JZ4780_CLK_KBC] = {
  491. "kbc", CGU_CLK_GATE,
  492. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  493. .gate = { CGU_REG_CLKGR0, 13 },
  494. },
  495. [JZ4780_CLK_SADC] = {
  496. "sadc", CGU_CLK_GATE,
  497. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  498. .gate = { CGU_REG_CLKGR0, 14 },
  499. },
  500. [JZ4780_CLK_UART0] = {
  501. "uart0", CGU_CLK_GATE,
  502. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  503. .gate = { CGU_REG_CLKGR0, 15 },
  504. },
  505. [JZ4780_CLK_UART1] = {
  506. "uart1", CGU_CLK_GATE,
  507. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  508. .gate = { CGU_REG_CLKGR0, 16 },
  509. },
  510. [JZ4780_CLK_UART2] = {
  511. "uart2", CGU_CLK_GATE,
  512. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  513. .gate = { CGU_REG_CLKGR0, 17 },
  514. },
  515. [JZ4780_CLK_UART3] = {
  516. "uart3", CGU_CLK_GATE,
  517. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  518. .gate = { CGU_REG_CLKGR0, 18 },
  519. },
  520. [JZ4780_CLK_SSI1] = {
  521. "ssi1", CGU_CLK_GATE,
  522. .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
  523. .gate = { CGU_REG_CLKGR0, 19 },
  524. },
  525. [JZ4780_CLK_SSI2] = {
  526. "ssi2", CGU_CLK_GATE,
  527. .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
  528. .gate = { CGU_REG_CLKGR0, 20 },
  529. },
  530. [JZ4780_CLK_PDMA] = {
  531. "pdma", CGU_CLK_GATE,
  532. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  533. .gate = { CGU_REG_CLKGR0, 21 },
  534. },
  535. [JZ4780_CLK_GPS] = {
  536. "gps", CGU_CLK_GATE,
  537. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  538. .gate = { CGU_REG_CLKGR0, 22 },
  539. },
  540. [JZ4780_CLK_MAC] = {
  541. "mac", CGU_CLK_GATE,
  542. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  543. .gate = { CGU_REG_CLKGR0, 23 },
  544. },
  545. [JZ4780_CLK_SMB2] = {
  546. "smb2", CGU_CLK_GATE,
  547. .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
  548. .gate = { CGU_REG_CLKGR0, 24 },
  549. },
  550. [JZ4780_CLK_CIM] = {
  551. "cim", CGU_CLK_GATE,
  552. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  553. .gate = { CGU_REG_CLKGR0, 26 },
  554. },
  555. [JZ4780_CLK_LCD] = {
  556. "lcd", CGU_CLK_GATE,
  557. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  558. .gate = { CGU_REG_CLKGR0, 28 },
  559. },
  560. [JZ4780_CLK_TVE] = {
  561. "tve", CGU_CLK_GATE,
  562. .parents = { JZ4780_CLK_LCD, -1, -1, -1 },
  563. .gate = { CGU_REG_CLKGR0, 27 },
  564. },
  565. [JZ4780_CLK_IPU] = {
  566. "ipu", CGU_CLK_GATE,
  567. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  568. .gate = { CGU_REG_CLKGR0, 29 },
  569. },
  570. [JZ4780_CLK_DDR0] = {
  571. "ddr0", CGU_CLK_GATE,
  572. .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
  573. .gate = { CGU_REG_CLKGR0, 30 },
  574. },
  575. [JZ4780_CLK_DDR1] = {
  576. "ddr1", CGU_CLK_GATE,
  577. .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
  578. .gate = { CGU_REG_CLKGR0, 31 },
  579. },
  580. [JZ4780_CLK_SMB3] = {
  581. "smb3", CGU_CLK_GATE,
  582. .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
  583. .gate = { CGU_REG_CLKGR1, 0 },
  584. },
  585. [JZ4780_CLK_TSSI1] = {
  586. "tssi1", CGU_CLK_GATE,
  587. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  588. .gate = { CGU_REG_CLKGR1, 1 },
  589. },
  590. [JZ4780_CLK_COMPRESS] = {
  591. "compress", CGU_CLK_GATE,
  592. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  593. .gate = { CGU_REG_CLKGR1, 5 },
  594. },
  595. [JZ4780_CLK_AIC1] = {
  596. "aic1", CGU_CLK_GATE,
  597. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  598. .gate = { CGU_REG_CLKGR1, 6 },
  599. },
  600. [JZ4780_CLK_GPVLC] = {
  601. "gpvlc", CGU_CLK_GATE,
  602. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  603. .gate = { CGU_REG_CLKGR1, 7 },
  604. },
  605. [JZ4780_CLK_OTG1] = {
  606. "otg1", CGU_CLK_GATE,
  607. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  608. .gate = { CGU_REG_CLKGR1, 8 },
  609. },
  610. [JZ4780_CLK_UART4] = {
  611. "uart4", CGU_CLK_GATE,
  612. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  613. .gate = { CGU_REG_CLKGR1, 10 },
  614. },
  615. [JZ4780_CLK_AHBMON] = {
  616. "ahb_mon", CGU_CLK_GATE,
  617. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  618. .gate = { CGU_REG_CLKGR1, 11 },
  619. },
  620. [JZ4780_CLK_SMB4] = {
  621. "smb4", CGU_CLK_GATE,
  622. .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
  623. .gate = { CGU_REG_CLKGR1, 12 },
  624. },
  625. [JZ4780_CLK_DES] = {
  626. "des", CGU_CLK_GATE,
  627. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  628. .gate = { CGU_REG_CLKGR1, 13 },
  629. },
  630. [JZ4780_CLK_X2D] = {
  631. "x2d", CGU_CLK_GATE,
  632. .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
  633. .gate = { CGU_REG_CLKGR1, 14 },
  634. },
  635. [JZ4780_CLK_CORE1] = {
  636. "core1", CGU_CLK_CUSTOM,
  637. .parents = { JZ4780_CLK_CPU, -1, -1, -1 },
  638. .custom = { &jz4780_core1_ops },
  639. },
  640. };
  641. static void __init jz4780_cgu_init(struct device_node *np)
  642. {
  643. int retval;
  644. cgu = ingenic_cgu_new(jz4780_cgu_clocks,
  645. ARRAY_SIZE(jz4780_cgu_clocks), np);
  646. if (!cgu) {
  647. pr_err("%s: failed to initialise CGU\n", __func__);
  648. return;
  649. }
  650. retval = ingenic_cgu_register_clocks(cgu);
  651. if (retval) {
  652. pr_err("%s: failed to register CGU Clocks\n", __func__);
  653. return;
  654. }
  655. ingenic_cgu_register_syscore_ops(cgu);
  656. }
  657. CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);