jz4770-cgu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * JZ4770 SoC CGU driver
  4. * Copyright 2018, Paul Cercueil <paul@crapouillou.net>
  5. */
  6. #include <linux/bitops.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/of.h>
  11. #include <dt-bindings/clock/jz4770-cgu.h>
  12. #include "cgu.h"
  13. #include "pm.h"
  14. /*
  15. * CPM registers offset address definition
  16. */
  17. #define CGU_REG_CPCCR 0x00
  18. #define CGU_REG_LCR 0x04
  19. #define CGU_REG_CPPCR0 0x10
  20. #define CGU_REG_CLKGR0 0x20
  21. #define CGU_REG_OPCR 0x24
  22. #define CGU_REG_CLKGR1 0x28
  23. #define CGU_REG_CPPCR1 0x30
  24. #define CGU_REG_USBPCR1 0x48
  25. #define CGU_REG_USBCDR 0x50
  26. #define CGU_REG_I2SCDR 0x60
  27. #define CGU_REG_LPCDR 0x64
  28. #define CGU_REG_MSC0CDR 0x68
  29. #define CGU_REG_UHCCDR 0x6c
  30. #define CGU_REG_SSICDR 0x74
  31. #define CGU_REG_CIMCDR 0x7c
  32. #define CGU_REG_GPSCDR 0x80
  33. #define CGU_REG_PCMCDR 0x84
  34. #define CGU_REG_GPUCDR 0x88
  35. #define CGU_REG_MSC1CDR 0xA4
  36. #define CGU_REG_MSC2CDR 0xA8
  37. #define CGU_REG_BCHCDR 0xAC
  38. /* bits within the OPCR register */
  39. #define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
  40. /* bits within the USBPCR1 register */
  41. #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
  42. static struct ingenic_cgu *cgu;
  43. static int jz4770_uhc_phy_enable(struct clk_hw *hw)
  44. {
  45. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  46. void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
  47. writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr);
  48. writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1);
  49. return 0;
  50. }
  51. static void jz4770_uhc_phy_disable(struct clk_hw *hw)
  52. {
  53. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  54. void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
  55. writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1);
  56. writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr);
  57. }
  58. static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw)
  59. {
  60. void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
  61. void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
  62. return !(readl(reg_opcr) & OPCR_SPENDH) &&
  63. (readl(reg_usbpcr1) & USBPCR1_UHC_POWER);
  64. }
  65. static const struct clk_ops jz4770_uhc_phy_ops = {
  66. .enable = jz4770_uhc_phy_enable,
  67. .disable = jz4770_uhc_phy_disable,
  68. .is_enabled = jz4770_uhc_phy_is_enabled,
  69. };
  70. static const s8 pll_od_encoding[8] = {
  71. 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
  72. };
  73. static const u8 jz4770_cgu_cpccr_div_table[] = {
  74. 1, 2, 3, 4, 6, 8, 12,
  75. };
  76. static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
  77. /* External clocks */
  78. [JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT },
  79. [JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
  80. /* PLLs */
  81. [JZ4770_CLK_PLL0] = {
  82. "pll0", CGU_CLK_PLL,
  83. .parents = { JZ4770_CLK_EXT },
  84. .pll = {
  85. .reg = CGU_REG_CPPCR0,
  86. .rate_multiplier = 1,
  87. .m_shift = 24,
  88. .m_bits = 7,
  89. .m_offset = 1,
  90. .n_shift = 18,
  91. .n_bits = 5,
  92. .n_offset = 1,
  93. .od_shift = 16,
  94. .od_bits = 2,
  95. .od_max = 8,
  96. .od_encoding = pll_od_encoding,
  97. .bypass_reg = CGU_REG_CPPCR0,
  98. .bypass_bit = 9,
  99. .enable_bit = 8,
  100. .stable_bit = 10,
  101. },
  102. },
  103. [JZ4770_CLK_PLL1] = {
  104. /* TODO: PLL1 can depend on PLL0 */
  105. "pll1", CGU_CLK_PLL,
  106. .parents = { JZ4770_CLK_EXT },
  107. .pll = {
  108. .reg = CGU_REG_CPPCR1,
  109. .rate_multiplier = 1,
  110. .m_shift = 24,
  111. .m_bits = 7,
  112. .m_offset = 1,
  113. .n_shift = 18,
  114. .n_bits = 5,
  115. .n_offset = 1,
  116. .od_shift = 16,
  117. .od_bits = 2,
  118. .od_max = 8,
  119. .od_encoding = pll_od_encoding,
  120. .bypass_reg = CGU_REG_CPPCR1,
  121. .no_bypass_bit = true,
  122. .enable_bit = 7,
  123. .stable_bit = 6,
  124. },
  125. },
  126. /* Main clocks */
  127. [JZ4770_CLK_CCLK] = {
  128. "cclk", CGU_CLK_DIV,
  129. .parents = { JZ4770_CLK_PLL0, },
  130. .div = {
  131. CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
  132. jz4770_cgu_cpccr_div_table,
  133. },
  134. },
  135. [JZ4770_CLK_H0CLK] = {
  136. "h0clk", CGU_CLK_DIV,
  137. .parents = { JZ4770_CLK_PLL0, },
  138. .div = {
  139. CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
  140. jz4770_cgu_cpccr_div_table,
  141. },
  142. },
  143. [JZ4770_CLK_H1CLK] = {
  144. "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
  145. .parents = { JZ4770_CLK_PLL0, },
  146. .div = {
  147. CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
  148. jz4770_cgu_cpccr_div_table,
  149. },
  150. .gate = { CGU_REG_CLKGR1, 7 },
  151. },
  152. [JZ4770_CLK_H2CLK] = {
  153. "h2clk", CGU_CLK_DIV,
  154. .parents = { JZ4770_CLK_PLL0, },
  155. .div = {
  156. CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
  157. jz4770_cgu_cpccr_div_table,
  158. },
  159. },
  160. [JZ4770_CLK_C1CLK] = {
  161. "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
  162. .parents = { JZ4770_CLK_PLL0, },
  163. .div = {
  164. CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
  165. jz4770_cgu_cpccr_div_table,
  166. },
  167. .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
  168. },
  169. [JZ4770_CLK_PCLK] = {
  170. "pclk", CGU_CLK_DIV,
  171. .parents = { JZ4770_CLK_PLL0, },
  172. .div = {
  173. CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
  174. jz4770_cgu_cpccr_div_table,
  175. },
  176. },
  177. /* Those divided clocks can connect to PLL0 or PLL1 */
  178. [JZ4770_CLK_MMC0_MUX] = {
  179. "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  180. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  181. .mux = { CGU_REG_MSC0CDR, 30, 1 },
  182. .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
  183. .gate = { CGU_REG_MSC0CDR, 31 },
  184. },
  185. [JZ4770_CLK_MMC1_MUX] = {
  186. "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  187. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  188. .mux = { CGU_REG_MSC1CDR, 30, 1 },
  189. .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
  190. .gate = { CGU_REG_MSC1CDR, 31 },
  191. },
  192. [JZ4770_CLK_MMC2_MUX] = {
  193. "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  194. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  195. .mux = { CGU_REG_MSC2CDR, 30, 1 },
  196. .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
  197. .gate = { CGU_REG_MSC2CDR, 31 },
  198. },
  199. [JZ4770_CLK_CIM] = {
  200. "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  201. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  202. .mux = { CGU_REG_CIMCDR, 31, 1 },
  203. .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
  204. .gate = { CGU_REG_CLKGR0, 26 },
  205. },
  206. [JZ4770_CLK_UHC] = {
  207. "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  208. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  209. .mux = { CGU_REG_UHCCDR, 29, 1 },
  210. .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
  211. .gate = { CGU_REG_CLKGR0, 24 },
  212. },
  213. [JZ4770_CLK_GPU] = {
  214. "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  215. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
  216. .mux = { CGU_REG_GPUCDR, 31, 1 },
  217. .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
  218. .gate = { CGU_REG_CLKGR1, 9 },
  219. },
  220. [JZ4770_CLK_BCH] = {
  221. "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  222. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  223. .mux = { CGU_REG_BCHCDR, 31, 1 },
  224. .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
  225. .gate = { CGU_REG_CLKGR0, 1 },
  226. },
  227. [JZ4770_CLK_LPCLK_MUX] = {
  228. "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  229. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  230. .mux = { CGU_REG_LPCDR, 29, 1 },
  231. .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
  232. .gate = { CGU_REG_CLKGR0, 28 },
  233. },
  234. [JZ4770_CLK_GPS] = {
  235. "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  236. .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
  237. .mux = { CGU_REG_GPSCDR, 31, 1 },
  238. .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
  239. .gate = { CGU_REG_CLKGR0, 22 },
  240. },
  241. /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
  242. [JZ4770_CLK_SSI_MUX] = {
  243. "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
  244. .parents = { JZ4770_CLK_EXT, -1,
  245. JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
  246. .mux = { CGU_REG_SSICDR, 30, 2 },
  247. .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
  248. },
  249. [JZ4770_CLK_PCM_MUX] = {
  250. "pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX,
  251. .parents = { JZ4770_CLK_EXT, -1,
  252. JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
  253. .mux = { CGU_REG_PCMCDR, 30, 2 },
  254. .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
  255. },
  256. [JZ4770_CLK_I2S] = {
  257. "i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  258. .parents = { JZ4770_CLK_EXT, -1,
  259. JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
  260. .mux = { CGU_REG_I2SCDR, 30, 2 },
  261. .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
  262. .gate = { CGU_REG_CLKGR1, 13 },
  263. },
  264. [JZ4770_CLK_OTG] = {
  265. "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
  266. .parents = { JZ4770_CLK_EXT, -1,
  267. JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
  268. .mux = { CGU_REG_USBCDR, 30, 2 },
  269. .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
  270. .gate = { CGU_REG_CLKGR0, 2 },
  271. },
  272. /* Gate-only clocks */
  273. [JZ4770_CLK_SSI0] = {
  274. "ssi0", CGU_CLK_GATE,
  275. .parents = { JZ4770_CLK_SSI_MUX, },
  276. .gate = { CGU_REG_CLKGR0, 4 },
  277. },
  278. [JZ4770_CLK_SSI1] = {
  279. "ssi1", CGU_CLK_GATE,
  280. .parents = { JZ4770_CLK_SSI_MUX, },
  281. .gate = { CGU_REG_CLKGR0, 19 },
  282. },
  283. [JZ4770_CLK_SSI2] = {
  284. "ssi2", CGU_CLK_GATE,
  285. .parents = { JZ4770_CLK_SSI_MUX, },
  286. .gate = { CGU_REG_CLKGR0, 20 },
  287. },
  288. [JZ4770_CLK_PCM0] = {
  289. "pcm0", CGU_CLK_GATE,
  290. .parents = { JZ4770_CLK_PCM_MUX, },
  291. .gate = { CGU_REG_CLKGR1, 8 },
  292. },
  293. [JZ4770_CLK_PCM1] = {
  294. "pcm1", CGU_CLK_GATE,
  295. .parents = { JZ4770_CLK_PCM_MUX, },
  296. .gate = { CGU_REG_CLKGR1, 10 },
  297. },
  298. [JZ4770_CLK_DMA] = {
  299. "dma", CGU_CLK_GATE,
  300. .parents = { JZ4770_CLK_H2CLK, },
  301. .gate = { CGU_REG_CLKGR0, 21 },
  302. },
  303. [JZ4770_CLK_I2C0] = {
  304. "i2c0", CGU_CLK_GATE,
  305. .parents = { JZ4770_CLK_EXT, },
  306. .gate = { CGU_REG_CLKGR0, 5 },
  307. },
  308. [JZ4770_CLK_I2C1] = {
  309. "i2c1", CGU_CLK_GATE,
  310. .parents = { JZ4770_CLK_EXT, },
  311. .gate = { CGU_REG_CLKGR0, 6 },
  312. },
  313. [JZ4770_CLK_I2C2] = {
  314. "i2c2", CGU_CLK_GATE,
  315. .parents = { JZ4770_CLK_EXT, },
  316. .gate = { CGU_REG_CLKGR1, 15 },
  317. },
  318. [JZ4770_CLK_UART0] = {
  319. "uart0", CGU_CLK_GATE,
  320. .parents = { JZ4770_CLK_EXT, },
  321. .gate = { CGU_REG_CLKGR0, 15 },
  322. },
  323. [JZ4770_CLK_UART1] = {
  324. "uart1", CGU_CLK_GATE,
  325. .parents = { JZ4770_CLK_EXT, },
  326. .gate = { CGU_REG_CLKGR0, 16 },
  327. },
  328. [JZ4770_CLK_UART2] = {
  329. "uart2", CGU_CLK_GATE,
  330. .parents = { JZ4770_CLK_EXT, },
  331. .gate = { CGU_REG_CLKGR0, 17 },
  332. },
  333. [JZ4770_CLK_UART3] = {
  334. "uart3", CGU_CLK_GATE,
  335. .parents = { JZ4770_CLK_EXT, },
  336. .gate = { CGU_REG_CLKGR0, 18 },
  337. },
  338. [JZ4770_CLK_IPU] = {
  339. "ipu", CGU_CLK_GATE,
  340. .parents = { JZ4770_CLK_H0CLK, },
  341. .gate = { CGU_REG_CLKGR0, 29 },
  342. },
  343. [JZ4770_CLK_ADC] = {
  344. "adc", CGU_CLK_GATE,
  345. .parents = { JZ4770_CLK_EXT, },
  346. .gate = { CGU_REG_CLKGR0, 14 },
  347. },
  348. [JZ4770_CLK_AIC] = {
  349. "aic", CGU_CLK_GATE,
  350. .parents = { JZ4770_CLK_EXT, },
  351. .gate = { CGU_REG_CLKGR0, 8 },
  352. },
  353. [JZ4770_CLK_AUX] = {
  354. "aux", CGU_CLK_GATE,
  355. .parents = { JZ4770_CLK_C1CLK, },
  356. .gate = { CGU_REG_CLKGR1, 14 },
  357. },
  358. [JZ4770_CLK_VPU] = {
  359. "vpu", CGU_CLK_GATE,
  360. .parents = { JZ4770_CLK_H1CLK, },
  361. .gate = { CGU_REG_LCR, 30, false, 150 },
  362. },
  363. [JZ4770_CLK_MMC0] = {
  364. "mmc0", CGU_CLK_GATE,
  365. .parents = { JZ4770_CLK_MMC0_MUX, },
  366. .gate = { CGU_REG_CLKGR0, 3 },
  367. },
  368. [JZ4770_CLK_MMC1] = {
  369. "mmc1", CGU_CLK_GATE,
  370. .parents = { JZ4770_CLK_MMC1_MUX, },
  371. .gate = { CGU_REG_CLKGR0, 11 },
  372. },
  373. [JZ4770_CLK_MMC2] = {
  374. "mmc2", CGU_CLK_GATE,
  375. .parents = { JZ4770_CLK_MMC2_MUX, },
  376. .gate = { CGU_REG_CLKGR0, 12 },
  377. },
  378. [JZ4770_CLK_OTG_PHY] = {
  379. "usb_phy", CGU_CLK_GATE,
  380. .parents = { JZ4770_CLK_OTG },
  381. .gate = { CGU_REG_OPCR, 7, true, 50 },
  382. },
  383. /* Custom clocks */
  384. [JZ4770_CLK_UHC_PHY] = {
  385. "uhc_phy", CGU_CLK_CUSTOM,
  386. .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
  387. .custom = { &jz4770_uhc_phy_ops },
  388. },
  389. [JZ4770_CLK_EXT512] = {
  390. "ext/512", CGU_CLK_FIXDIV,
  391. .parents = { JZ4770_CLK_EXT },
  392. .fixdiv = { 512 },
  393. },
  394. [JZ4770_CLK_RTC] = {
  395. "rtc", CGU_CLK_MUX,
  396. .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, },
  397. .mux = { CGU_REG_OPCR, 2, 1},
  398. },
  399. };
  400. static void __init jz4770_cgu_init(struct device_node *np)
  401. {
  402. int retval;
  403. cgu = ingenic_cgu_new(jz4770_cgu_clocks,
  404. ARRAY_SIZE(jz4770_cgu_clocks), np);
  405. if (!cgu) {
  406. pr_err("%s: failed to initialise CGU\n", __func__);
  407. return;
  408. }
  409. retval = ingenic_cgu_register_clocks(cgu);
  410. if (retval)
  411. pr_err("%s: failed to register CGU Clocks\n", __func__);
  412. ingenic_cgu_register_syscore_ops(cgu);
  413. }
  414. /* We only probe via devicetree, no need for a platform driver */
  415. CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);