jz4725b-cgu.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Ingenic JZ4725B SoC CGU driver
  4. *
  5. * Copyright (C) 2018 Paul Cercueil
  6. * Author: Paul Cercueil <paul@crapouillou.net>
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/delay.h>
  10. #include <linux/of.h>
  11. #include <dt-bindings/clock/jz4725b-cgu.h>
  12. #include "cgu.h"
  13. #include "pm.h"
  14. /* CGU register offsets */
  15. #define CGU_REG_CPCCR 0x00
  16. #define CGU_REG_LCR 0x04
  17. #define CGU_REG_CPPCR 0x10
  18. #define CGU_REG_CLKGR 0x20
  19. #define CGU_REG_OPCR 0x24
  20. #define CGU_REG_I2SCDR 0x60
  21. #define CGU_REG_LPCDR 0x64
  22. #define CGU_REG_MSCCDR 0x68
  23. #define CGU_REG_SSICDR 0x74
  24. #define CGU_REG_CIMCDR 0x78
  25. /* bits within the LCR register */
  26. #define LCR_SLEEP BIT(0)
  27. static struct ingenic_cgu *cgu;
  28. static const s8 pll_od_encoding[4] = {
  29. 0x0, 0x1, -1, 0x3,
  30. };
  31. static const u8 jz4725b_cgu_cpccr_div_table[] = {
  32. 1, 2, 3, 4, 6, 8,
  33. };
  34. static const u8 jz4725b_cgu_pll_half_div_table[] = {
  35. 2, 1,
  36. };
  37. static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
  38. /* External clocks */
  39. [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
  40. [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
  41. [JZ4725B_CLK_PLL] = {
  42. "pll", CGU_CLK_PLL,
  43. .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  44. .pll = {
  45. .reg = CGU_REG_CPPCR,
  46. .rate_multiplier = 1,
  47. .m_shift = 23,
  48. .m_bits = 9,
  49. .m_offset = 2,
  50. .n_shift = 18,
  51. .n_bits = 5,
  52. .n_offset = 2,
  53. .od_shift = 16,
  54. .od_bits = 2,
  55. .od_max = 4,
  56. .od_encoding = pll_od_encoding,
  57. .stable_bit = 10,
  58. .bypass_reg = CGU_REG_CPPCR,
  59. .bypass_bit = 9,
  60. .enable_bit = 8,
  61. },
  62. },
  63. /* Muxes & dividers */
  64. [JZ4725B_CLK_PLL_HALF] = {
  65. "pll half", CGU_CLK_DIV,
  66. .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  67. .div = {
  68. CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
  69. jz4725b_cgu_pll_half_div_table,
  70. },
  71. },
  72. [JZ4725B_CLK_CCLK] = {
  73. "cclk", CGU_CLK_DIV,
  74. .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  75. .div = {
  76. CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
  77. jz4725b_cgu_cpccr_div_table,
  78. },
  79. },
  80. [JZ4725B_CLK_HCLK] = {
  81. "hclk", CGU_CLK_DIV,
  82. .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  83. .div = {
  84. CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
  85. jz4725b_cgu_cpccr_div_table,
  86. },
  87. },
  88. [JZ4725B_CLK_PCLK] = {
  89. "pclk", CGU_CLK_DIV,
  90. .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  91. .div = {
  92. CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
  93. jz4725b_cgu_cpccr_div_table,
  94. },
  95. },
  96. [JZ4725B_CLK_MCLK] = {
  97. "mclk", CGU_CLK_DIV,
  98. .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  99. .div = {
  100. CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
  101. jz4725b_cgu_cpccr_div_table,
  102. },
  103. },
  104. [JZ4725B_CLK_IPU] = {
  105. "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
  106. .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
  107. .div = {
  108. CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
  109. jz4725b_cgu_cpccr_div_table,
  110. },
  111. .gate = { CGU_REG_CLKGR, 13 },
  112. },
  113. [JZ4725B_CLK_LCD] = {
  114. "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
  115. .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
  116. .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
  117. .gate = { CGU_REG_CLKGR, 9 },
  118. },
  119. [JZ4725B_CLK_I2S] = {
  120. "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
  121. .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
  122. .mux = { CGU_REG_CPCCR, 31, 1 },
  123. .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
  124. },
  125. [JZ4725B_CLK_SPI] = {
  126. "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
  127. .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
  128. .mux = { CGU_REG_SSICDR, 31, 1 },
  129. .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
  130. .gate = { CGU_REG_CLKGR, 4 },
  131. },
  132. [JZ4725B_CLK_MMC_MUX] = {
  133. "mmc_mux", CGU_CLK_DIV,
  134. .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
  135. .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
  136. },
  137. [JZ4725B_CLK_UDC] = {
  138. "udc", CGU_CLK_MUX | CGU_CLK_DIV,
  139. .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
  140. .mux = { CGU_REG_CPCCR, 29, 1 },
  141. .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
  142. },
  143. /* Gate-only clocks */
  144. [JZ4725B_CLK_UART] = {
  145. "uart", CGU_CLK_GATE,
  146. .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  147. .gate = { CGU_REG_CLKGR, 0 },
  148. },
  149. [JZ4725B_CLK_DMA] = {
  150. "dma", CGU_CLK_GATE,
  151. .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
  152. .gate = { CGU_REG_CLKGR, 12 },
  153. },
  154. [JZ4725B_CLK_ADC] = {
  155. "adc", CGU_CLK_GATE,
  156. .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  157. .gate = { CGU_REG_CLKGR, 7 },
  158. },
  159. [JZ4725B_CLK_I2C] = {
  160. "i2c", CGU_CLK_GATE,
  161. .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  162. .gate = { CGU_REG_CLKGR, 3 },
  163. },
  164. [JZ4725B_CLK_AIC] = {
  165. "aic", CGU_CLK_GATE,
  166. .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  167. .gate = { CGU_REG_CLKGR, 5 },
  168. },
  169. [JZ4725B_CLK_MMC0] = {
  170. "mmc0", CGU_CLK_GATE,
  171. .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
  172. .gate = { CGU_REG_CLKGR, 6 },
  173. },
  174. [JZ4725B_CLK_MMC1] = {
  175. "mmc1", CGU_CLK_GATE,
  176. .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
  177. .gate = { CGU_REG_CLKGR, 16 },
  178. },
  179. [JZ4725B_CLK_BCH] = {
  180. "bch", CGU_CLK_GATE,
  181. .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
  182. .gate = { CGU_REG_CLKGR, 11 },
  183. },
  184. [JZ4725B_CLK_TCU] = {
  185. "tcu", CGU_CLK_GATE,
  186. .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
  187. .gate = { CGU_REG_CLKGR, 1 },
  188. },
  189. [JZ4725B_CLK_EXT512] = {
  190. "ext/512", CGU_CLK_FIXDIV,
  191. .parents = { JZ4725B_CLK_EXT },
  192. /* Doc calls it EXT512, but it seems to be /256... */
  193. .fixdiv = { 256 },
  194. },
  195. [JZ4725B_CLK_RTC] = {
  196. "rtc", CGU_CLK_MUX,
  197. .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
  198. .mux = { CGU_REG_OPCR, 2, 1},
  199. },
  200. [JZ4725B_CLK_UDC_PHY] = {
  201. "udc_phy", CGU_CLK_GATE,
  202. .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
  203. .gate = { CGU_REG_OPCR, 6, true },
  204. },
  205. };
  206. static void __init jz4725b_cgu_init(struct device_node *np)
  207. {
  208. int retval;
  209. cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
  210. ARRAY_SIZE(jz4725b_cgu_clocks), np);
  211. if (!cgu) {
  212. pr_err("%s: failed to initialise CGU\n", __func__);
  213. return;
  214. }
  215. retval = ingenic_cgu_register_clocks(cgu);
  216. if (retval)
  217. pr_err("%s: failed to register CGU Clocks\n", __func__);
  218. ingenic_cgu_register_syscore_ops(cgu);
  219. }
  220. CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);