cgu.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Ingenic SoC CGU driver
  4. *
  5. * Copyright (c) 2013-2015 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@mips.com>
  7. */
  8. #ifndef __DRIVERS_CLK_INGENIC_CGU_H__
  9. #define __DRIVERS_CLK_INGENIC_CGU_H__
  10. #include <linux/bitops.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/of.h>
  13. #include <linux/spinlock.h>
  14. /**
  15. * struct ingenic_cgu_pll_info - information about a PLL
  16. * @reg: the offset of the PLL's control register within the CGU
  17. * @rate_multiplier: the multiplier needed by pll rate calculation
  18. * @m_shift: the number of bits to shift the multiplier value by (ie. the
  19. * index of the lowest bit of the multiplier value in the PLL's
  20. * control register)
  21. * @m_bits: the size of the multiplier field in bits
  22. * @m_offset: the multiplier value which encodes to 0 in the PLL's control
  23. * register
  24. * @n_shift: the number of bits to shift the divider value by (ie. the
  25. * index of the lowest bit of the divider value in the PLL's
  26. * control register)
  27. * @n_bits: the size of the divider field in bits
  28. * @n_offset: the divider value which encodes to 0 in the PLL's control
  29. * register
  30. * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
  31. * the index of the lowest bit of the post-VCO divider value in
  32. * the PLL's control register)
  33. * @od_bits: the size of the post-VCO divider field in bits
  34. * @od_max: the maximum post-VCO divider value
  35. * @od_encoding: a pointer to an array mapping post-VCO divider values to
  36. * their encoded values in the PLL control register, or -1 for
  37. * unsupported values
  38. * @bypass_reg: the offset of the bypass control register within the CGU
  39. * @bypass_bit: the index of the bypass bit in the PLL control register
  40. * @enable_bit: the index of the enable bit in the PLL control register
  41. * @stable_bit: the index of the stable bit in the PLL control register
  42. * @no_bypass_bit: if set, the PLL has no bypass functionality
  43. */
  44. struct ingenic_cgu_pll_info {
  45. unsigned reg;
  46. unsigned rate_multiplier;
  47. const s8 *od_encoding;
  48. u8 m_shift, m_bits, m_offset;
  49. u8 n_shift, n_bits, n_offset;
  50. u8 od_shift, od_bits, od_max;
  51. unsigned bypass_reg;
  52. u8 bypass_bit;
  53. u8 enable_bit;
  54. u8 stable_bit;
  55. bool no_bypass_bit;
  56. };
  57. /**
  58. * struct ingenic_cgu_mux_info - information about a clock mux
  59. * @reg: offset of the mux control register within the CGU
  60. * @shift: number of bits to shift the mux value by (ie. the index of
  61. * the lowest bit of the mux value within its control register)
  62. * @bits: the size of the mux value in bits
  63. */
  64. struct ingenic_cgu_mux_info {
  65. unsigned reg;
  66. u8 shift;
  67. u8 bits;
  68. };
  69. /**
  70. * struct ingenic_cgu_div_info - information about a divider
  71. * @reg: offset of the divider control register within the CGU
  72. * @shift: number of bits to left shift the divide value by (ie. the index of
  73. * the lowest bit of the divide value within its control register)
  74. * @div: number to divide the divider value by (i.e. if the
  75. * effective divider value is the value written to the register
  76. * multiplied by some constant)
  77. * @bits: the size of the divide value in bits
  78. * @ce_bit: the index of the change enable bit within reg, or -1 if there
  79. * isn't one
  80. * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
  81. * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
  82. * @div_table: optional table to map the value read from the register to the
  83. * actual divider value
  84. */
  85. struct ingenic_cgu_div_info {
  86. unsigned reg;
  87. u8 shift;
  88. u8 div;
  89. u8 bits;
  90. s8 ce_bit;
  91. s8 busy_bit;
  92. s8 stop_bit;
  93. const u8 *div_table;
  94. };
  95. /**
  96. * struct ingenic_cgu_fixdiv_info - information about a fixed divider
  97. * @div: the divider applied to the parent clock
  98. */
  99. struct ingenic_cgu_fixdiv_info {
  100. unsigned div;
  101. };
  102. /**
  103. * struct ingenic_cgu_gate_info - information about a clock gate
  104. * @reg: offset of the gate control register within the CGU
  105. * @bit: offset of the bit in the register that controls the gate
  106. * @clear_to_gate: if set, the clock is gated when the bit is cleared
  107. * @delay_us: delay in microseconds after which the clock is considered stable
  108. */
  109. struct ingenic_cgu_gate_info {
  110. unsigned reg;
  111. u8 bit;
  112. bool clear_to_gate;
  113. u16 delay_us;
  114. };
  115. /**
  116. * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
  117. * @clk_ops: custom clock operation callbacks
  118. */
  119. struct ingenic_cgu_custom_info {
  120. const struct clk_ops *clk_ops;
  121. };
  122. /**
  123. * struct ingenic_cgu_clk_info - information about a clock
  124. * @name: name of the clock
  125. * @type: a bitmask formed from CGU_CLK_* values
  126. * @parents: an array of the indices of potential parents of this clock
  127. * within the clock_info array of the CGU, or -1 in entries
  128. * which correspond to no valid parent
  129. * @pll: information valid if type includes CGU_CLK_PLL
  130. * @gate: information valid if type includes CGU_CLK_GATE
  131. * @mux: information valid if type includes CGU_CLK_MUX
  132. * @div: information valid if type includes CGU_CLK_DIV
  133. * @fixdiv: information valid if type includes CGU_CLK_FIXDIV
  134. * @custom: information valid if type includes CGU_CLK_CUSTOM
  135. */
  136. struct ingenic_cgu_clk_info {
  137. const char *name;
  138. enum {
  139. CGU_CLK_NONE = 0,
  140. CGU_CLK_EXT = BIT(0),
  141. CGU_CLK_PLL = BIT(1),
  142. CGU_CLK_GATE = BIT(2),
  143. CGU_CLK_MUX = BIT(3),
  144. CGU_CLK_MUX_GLITCHFREE = BIT(4),
  145. CGU_CLK_DIV = BIT(5),
  146. CGU_CLK_FIXDIV = BIT(6),
  147. CGU_CLK_CUSTOM = BIT(7),
  148. } type;
  149. int parents[4];
  150. union {
  151. struct ingenic_cgu_pll_info pll;
  152. struct {
  153. struct ingenic_cgu_gate_info gate;
  154. struct ingenic_cgu_mux_info mux;
  155. struct ingenic_cgu_div_info div;
  156. struct ingenic_cgu_fixdiv_info fixdiv;
  157. };
  158. struct ingenic_cgu_custom_info custom;
  159. };
  160. };
  161. /**
  162. * struct ingenic_cgu - data about the CGU
  163. * @np: the device tree node that caused the CGU to be probed
  164. * @base: the ioremap'ed base address of the CGU registers
  165. * @clock_info: an array containing information about implemented clocks
  166. * @clocks: used to provide clocks to DT, allows lookup of struct clk*
  167. * @lock: lock to be held whilst manipulating CGU registers
  168. */
  169. struct ingenic_cgu {
  170. struct device_node *np;
  171. void __iomem *base;
  172. const struct ingenic_cgu_clk_info *clock_info;
  173. struct clk_onecell_data clocks;
  174. spinlock_t lock;
  175. };
  176. /**
  177. * struct ingenic_clk - private data for a clock
  178. * @hw: see Documentation/driver-api/clk.rst
  179. * @cgu: a pointer to the CGU data
  180. * @idx: the index of this clock in cgu->clock_info
  181. */
  182. struct ingenic_clk {
  183. struct clk_hw hw;
  184. struct ingenic_cgu *cgu;
  185. unsigned idx;
  186. };
  187. #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw)
  188. /**
  189. * ingenic_cgu_new() - create a new CGU instance
  190. * @clock_info: an array of clock information structures describing the clocks
  191. * which are implemented by the CGU
  192. * @num_clocks: the number of entries in clock_info
  193. * @np: the device tree node which causes this CGU to be probed
  194. *
  195. * Return: a pointer to the CGU instance if initialisation is successful,
  196. * otherwise NULL.
  197. */
  198. struct ingenic_cgu *
  199. ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info,
  200. unsigned num_clocks, struct device_node *np);
  201. /**
  202. * ingenic_cgu_register_clocks() - Registers the clocks
  203. * @cgu: pointer to cgu data
  204. *
  205. * Register the clocks described by the CGU with the common clock framework.
  206. *
  207. * Return: 0 on success or -errno if unsuccesful.
  208. */
  209. int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
  210. #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */