clk-sscg-pll.c 13 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright 2018 NXP.
  4. *
  5. * This driver supports the SCCG plls found in the imx8m SOCs
  6. *
  7. * Documentation for this SCCG pll can be found at:
  8. * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/err.h>
  12. #include <linux/export.h>
  13. #include <linux/io.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/slab.h>
  16. #include <linux/bitfield.h>
  17. #include "clk.h"
  18. /* PLL CFGs */
  19. #define PLL_CFG0 0x0
  20. #define PLL_CFG1 0x4
  21. #define PLL_CFG2 0x8
  22. #define PLL_DIVF1_MASK GENMASK(18, 13)
  23. #define PLL_DIVF2_MASK GENMASK(12, 7)
  24. #define PLL_DIVR1_MASK GENMASK(27, 25)
  25. #define PLL_DIVR2_MASK GENMASK(24, 19)
  26. #define PLL_DIVQ_MASK GENMASK(6, 1)
  27. #define PLL_REF_MASK GENMASK(2, 0)
  28. #define PLL_LOCK_MASK BIT(31)
  29. #define PLL_PD_MASK BIT(7)
  30. /* These are the specification limits for the SSCG PLL */
  31. #define PLL_REF_MIN_FREQ 25000000UL
  32. #define PLL_REF_MAX_FREQ 235000000UL
  33. #define PLL_STAGE1_MIN_FREQ 1600000000UL
  34. #define PLL_STAGE1_MAX_FREQ 2400000000UL
  35. #define PLL_STAGE1_REF_MIN_FREQ 25000000UL
  36. #define PLL_STAGE1_REF_MAX_FREQ 54000000UL
  37. #define PLL_STAGE2_MIN_FREQ 1200000000UL
  38. #define PLL_STAGE2_MAX_FREQ 2400000000UL
  39. #define PLL_STAGE2_REF_MIN_FREQ 54000000UL
  40. #define PLL_STAGE2_REF_MAX_FREQ 75000000UL
  41. #define PLL_OUT_MIN_FREQ 20000000UL
  42. #define PLL_OUT_MAX_FREQ 1200000000UL
  43. #define PLL_DIVR1_MAX 7
  44. #define PLL_DIVR2_MAX 63
  45. #define PLL_DIVF1_MAX 63
  46. #define PLL_DIVF2_MAX 63
  47. #define PLL_DIVQ_MAX 63
  48. #define PLL_BYPASS_NONE 0x0
  49. #define PLL_BYPASS1 0x2
  50. #define PLL_BYPASS2 0x1
  51. #define SSCG_PLL_BYPASS1_MASK BIT(5)
  52. #define SSCG_PLL_BYPASS2_MASK BIT(4)
  53. #define SSCG_PLL_BYPASS_MASK GENMASK(5, 4)
  54. #define PLL_SCCG_LOCK_TIMEOUT 70
  55. struct clk_sscg_pll_setup {
  56. int divr1, divf1;
  57. int divr2, divf2;
  58. int divq;
  59. int bypass;
  60. uint64_t vco1;
  61. uint64_t vco2;
  62. uint64_t fout;
  63. uint64_t ref;
  64. uint64_t ref_div1;
  65. uint64_t ref_div2;
  66. uint64_t fout_request;
  67. int fout_error;
  68. };
  69. struct clk_sscg_pll {
  70. struct clk_hw hw;
  71. const struct clk_ops ops;
  72. void __iomem *base;
  73. struct clk_sscg_pll_setup setup;
  74. u8 parent;
  75. u8 bypass1;
  76. u8 bypass2;
  77. };
  78. #define to_clk_sscg_pll(_hw) container_of(_hw, struct clk_sscg_pll, hw)
  79. static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll)
  80. {
  81. u32 val;
  82. val = readl_relaxed(pll->base + PLL_CFG0);
  83. /* don't wait for lock if all plls are bypassed */
  84. if (!(val & SSCG_PLL_BYPASS2_MASK))
  85. return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
  86. 0, PLL_SCCG_LOCK_TIMEOUT);
  87. return 0;
  88. }
  89. static int clk_sscg_pll2_check_match(struct clk_sscg_pll_setup *setup,
  90. struct clk_sscg_pll_setup *temp_setup)
  91. {
  92. int new_diff = temp_setup->fout - temp_setup->fout_request;
  93. int diff = temp_setup->fout_error;
  94. if (abs(diff) > abs(new_diff)) {
  95. temp_setup->fout_error = new_diff;
  96. memcpy(setup, temp_setup, sizeof(struct clk_sscg_pll_setup));
  97. if (temp_setup->fout_request == temp_setup->fout)
  98. return 0;
  99. }
  100. return -1;
  101. }
  102. static int clk_sscg_divq_lookup(struct clk_sscg_pll_setup *setup,
  103. struct clk_sscg_pll_setup *temp_setup)
  104. {
  105. int ret = -EINVAL;
  106. for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX;
  107. temp_setup->divq++) {
  108. temp_setup->vco2 = temp_setup->vco1;
  109. do_div(temp_setup->vco2, temp_setup->divr2 + 1);
  110. temp_setup->vco2 *= 2;
  111. temp_setup->vco2 *= temp_setup->divf2 + 1;
  112. if (temp_setup->vco2 >= PLL_STAGE2_MIN_FREQ &&
  113. temp_setup->vco2 <= PLL_STAGE2_MAX_FREQ) {
  114. temp_setup->fout = temp_setup->vco2;
  115. do_div(temp_setup->fout, 2 * (temp_setup->divq + 1));
  116. ret = clk_sscg_pll2_check_match(setup, temp_setup);
  117. if (!ret) {
  118. temp_setup->bypass = PLL_BYPASS1;
  119. return ret;
  120. }
  121. }
  122. }
  123. return ret;
  124. }
  125. static int clk_sscg_divf2_lookup(struct clk_sscg_pll_setup *setup,
  126. struct clk_sscg_pll_setup *temp_setup)
  127. {
  128. int ret = -EINVAL;
  129. for (temp_setup->divf2 = 0; temp_setup->divf2 <= PLL_DIVF2_MAX;
  130. temp_setup->divf2++) {
  131. ret = clk_sscg_divq_lookup(setup, temp_setup);
  132. if (!ret)
  133. return ret;
  134. }
  135. return ret;
  136. }
  137. static int clk_sscg_divr2_lookup(struct clk_sscg_pll_setup *setup,
  138. struct clk_sscg_pll_setup *temp_setup)
  139. {
  140. int ret = -EINVAL;
  141. for (temp_setup->divr2 = 0; temp_setup->divr2 <= PLL_DIVR2_MAX;
  142. temp_setup->divr2++) {
  143. temp_setup->ref_div2 = temp_setup->vco1;
  144. do_div(temp_setup->ref_div2, temp_setup->divr2 + 1);
  145. if (temp_setup->ref_div2 >= PLL_STAGE2_REF_MIN_FREQ &&
  146. temp_setup->ref_div2 <= PLL_STAGE2_REF_MAX_FREQ) {
  147. ret = clk_sscg_divf2_lookup(setup, temp_setup);
  148. if (!ret)
  149. return ret;
  150. }
  151. }
  152. return ret;
  153. }
  154. static int clk_sscg_pll2_find_setup(struct clk_sscg_pll_setup *setup,
  155. struct clk_sscg_pll_setup *temp_setup,
  156. uint64_t ref)
  157. {
  158. int ret;
  159. if (ref < PLL_STAGE1_MIN_FREQ || ref > PLL_STAGE1_MAX_FREQ)
  160. return -EINVAL;
  161. temp_setup->vco1 = ref;
  162. ret = clk_sscg_divr2_lookup(setup, temp_setup);
  163. return ret;
  164. }
  165. static int clk_sscg_divf1_lookup(struct clk_sscg_pll_setup *setup,
  166. struct clk_sscg_pll_setup *temp_setup)
  167. {
  168. int ret = -EINVAL;
  169. for (temp_setup->divf1 = 0; temp_setup->divf1 <= PLL_DIVF1_MAX;
  170. temp_setup->divf1++) {
  171. uint64_t vco1 = temp_setup->ref;
  172. do_div(vco1, temp_setup->divr1 + 1);
  173. vco1 *= 2;
  174. vco1 *= temp_setup->divf1 + 1;
  175. ret = clk_sscg_pll2_find_setup(setup, temp_setup, vco1);
  176. if (!ret) {
  177. temp_setup->bypass = PLL_BYPASS_NONE;
  178. return ret;
  179. }
  180. }
  181. return ret;
  182. }
  183. static int clk_sscg_divr1_lookup(struct clk_sscg_pll_setup *setup,
  184. struct clk_sscg_pll_setup *temp_setup)
  185. {
  186. int ret = -EINVAL;
  187. for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX;
  188. temp_setup->divr1++) {
  189. temp_setup->ref_div1 = temp_setup->ref;
  190. do_div(temp_setup->ref_div1, temp_setup->divr1 + 1);
  191. if (temp_setup->ref_div1 >= PLL_STAGE1_REF_MIN_FREQ &&
  192. temp_setup->ref_div1 <= PLL_STAGE1_REF_MAX_FREQ) {
  193. ret = clk_sscg_divf1_lookup(setup, temp_setup);
  194. if (!ret)
  195. return ret;
  196. }
  197. }
  198. return ret;
  199. }
  200. static int clk_sscg_pll1_find_setup(struct clk_sscg_pll_setup *setup,
  201. struct clk_sscg_pll_setup *temp_setup,
  202. uint64_t ref)
  203. {
  204. int ret;
  205. if (ref < PLL_REF_MIN_FREQ || ref > PLL_REF_MAX_FREQ)
  206. return -EINVAL;
  207. temp_setup->ref = ref;
  208. ret = clk_sscg_divr1_lookup(setup, temp_setup);
  209. return ret;
  210. }
  211. static int clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup,
  212. uint64_t prate,
  213. uint64_t rate, int try_bypass)
  214. {
  215. struct clk_sscg_pll_setup temp_setup;
  216. int ret = -EINVAL;
  217. memset(&temp_setup, 0, sizeof(struct clk_sscg_pll_setup));
  218. memset(setup, 0, sizeof(struct clk_sscg_pll_setup));
  219. temp_setup.fout_error = PLL_OUT_MAX_FREQ;
  220. temp_setup.fout_request = rate;
  221. switch (try_bypass) {
  222. case PLL_BYPASS2:
  223. if (prate == rate) {
  224. setup->bypass = PLL_BYPASS2;
  225. setup->fout = rate;
  226. ret = 0;
  227. }
  228. break;
  229. case PLL_BYPASS1:
  230. ret = clk_sscg_pll2_find_setup(setup, &temp_setup, prate);
  231. break;
  232. case PLL_BYPASS_NONE:
  233. ret = clk_sscg_pll1_find_setup(setup, &temp_setup, prate);
  234. break;
  235. }
  236. return ret;
  237. }
  238. static int clk_sscg_pll_is_prepared(struct clk_hw *hw)
  239. {
  240. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  241. u32 val = readl_relaxed(pll->base + PLL_CFG0);
  242. return (val & PLL_PD_MASK) ? 0 : 1;
  243. }
  244. static int clk_sscg_pll_prepare(struct clk_hw *hw)
  245. {
  246. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  247. u32 val;
  248. val = readl_relaxed(pll->base + PLL_CFG0);
  249. val &= ~PLL_PD_MASK;
  250. writel_relaxed(val, pll->base + PLL_CFG0);
  251. return clk_sscg_pll_wait_lock(pll);
  252. }
  253. static void clk_sscg_pll_unprepare(struct clk_hw *hw)
  254. {
  255. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  256. u32 val;
  257. val = readl_relaxed(pll->base + PLL_CFG0);
  258. val |= PLL_PD_MASK;
  259. writel_relaxed(val, pll->base + PLL_CFG0);
  260. }
  261. static unsigned long clk_sscg_pll_recalc_rate(struct clk_hw *hw,
  262. unsigned long parent_rate)
  263. {
  264. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  265. u32 val, divr1, divf1, divr2, divf2, divq;
  266. u64 temp64;
  267. val = readl_relaxed(pll->base + PLL_CFG2);
  268. divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
  269. divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
  270. divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
  271. divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
  272. divq = FIELD_GET(PLL_DIVQ_MASK, val);
  273. temp64 = parent_rate;
  274. val = readl(pll->base + PLL_CFG0);
  275. if (val & SSCG_PLL_BYPASS2_MASK) {
  276. temp64 = parent_rate;
  277. } else if (val & SSCG_PLL_BYPASS1_MASK) {
  278. temp64 *= divf2;
  279. do_div(temp64, (divr2 + 1) * (divq + 1));
  280. } else {
  281. temp64 *= 2;
  282. temp64 *= (divf1 + 1) * (divf2 + 1);
  283. do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1));
  284. }
  285. return temp64;
  286. }
  287. static int clk_sscg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  288. unsigned long parent_rate)
  289. {
  290. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  291. struct clk_sscg_pll_setup *setup = &pll->setup;
  292. u32 val;
  293. /* set bypass here too since the parent might be the same */
  294. val = readl(pll->base + PLL_CFG0);
  295. val &= ~SSCG_PLL_BYPASS_MASK;
  296. val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
  297. writel(val, pll->base + PLL_CFG0);
  298. val = readl_relaxed(pll->base + PLL_CFG2);
  299. val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
  300. val &= ~(PLL_DIVR1_MASK | PLL_DIVR2_MASK | PLL_DIVQ_MASK);
  301. val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1);
  302. val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2);
  303. val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1);
  304. val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2);
  305. val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq);
  306. writel_relaxed(val, pll->base + PLL_CFG2);
  307. return clk_sscg_pll_wait_lock(pll);
  308. }
  309. static u8 clk_sscg_pll_get_parent(struct clk_hw *hw)
  310. {
  311. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  312. u32 val;
  313. u8 ret = pll->parent;
  314. val = readl(pll->base + PLL_CFG0);
  315. if (val & SSCG_PLL_BYPASS2_MASK)
  316. ret = pll->bypass2;
  317. else if (val & SSCG_PLL_BYPASS1_MASK)
  318. ret = pll->bypass1;
  319. return ret;
  320. }
  321. static int clk_sscg_pll_set_parent(struct clk_hw *hw, u8 index)
  322. {
  323. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  324. u32 val;
  325. val = readl(pll->base + PLL_CFG0);
  326. val &= ~SSCG_PLL_BYPASS_MASK;
  327. val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
  328. writel(val, pll->base + PLL_CFG0);
  329. return clk_sscg_pll_wait_lock(pll);
  330. }
  331. static int __clk_sscg_pll_determine_rate(struct clk_hw *hw,
  332. struct clk_rate_request *req,
  333. uint64_t min,
  334. uint64_t max,
  335. uint64_t rate,
  336. int bypass)
  337. {
  338. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  339. struct clk_sscg_pll_setup *setup = &pll->setup;
  340. struct clk_hw *parent_hw = NULL;
  341. int bypass_parent_index;
  342. int ret;
  343. req->max_rate = max;
  344. req->min_rate = min;
  345. switch (bypass) {
  346. case PLL_BYPASS2:
  347. bypass_parent_index = pll->bypass2;
  348. break;
  349. case PLL_BYPASS1:
  350. bypass_parent_index = pll->bypass1;
  351. break;
  352. default:
  353. bypass_parent_index = pll->parent;
  354. break;
  355. }
  356. parent_hw = clk_hw_get_parent_by_index(hw, bypass_parent_index);
  357. ret = __clk_determine_rate(parent_hw, req);
  358. if (!ret) {
  359. ret = clk_sscg_pll_find_setup(setup, req->rate,
  360. rate, bypass);
  361. }
  362. req->best_parent_hw = parent_hw;
  363. req->best_parent_rate = req->rate;
  364. req->rate = setup->fout;
  365. return ret;
  366. }
  367. static int clk_sscg_pll_determine_rate(struct clk_hw *hw,
  368. struct clk_rate_request *req)
  369. {
  370. struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
  371. struct clk_sscg_pll_setup *setup = &pll->setup;
  372. uint64_t rate = req->rate;
  373. uint64_t min = req->min_rate;
  374. uint64_t max = req->max_rate;
  375. int ret;
  376. if (rate < PLL_OUT_MIN_FREQ || rate > PLL_OUT_MAX_FREQ)
  377. return -EINVAL;
  378. ret = __clk_sscg_pll_determine_rate(hw, req, req->rate, req->rate,
  379. rate, PLL_BYPASS2);
  380. if (!ret)
  381. return ret;
  382. ret = __clk_sscg_pll_determine_rate(hw, req, PLL_STAGE1_REF_MIN_FREQ,
  383. PLL_STAGE1_REF_MAX_FREQ, rate,
  384. PLL_BYPASS1);
  385. if (!ret)
  386. return ret;
  387. ret = __clk_sscg_pll_determine_rate(hw, req, PLL_REF_MIN_FREQ,
  388. PLL_REF_MAX_FREQ, rate,
  389. PLL_BYPASS_NONE);
  390. if (!ret)
  391. return ret;
  392. if (setup->fout >= min && setup->fout <= max)
  393. ret = 0;
  394. return ret;
  395. }
  396. static const struct clk_ops clk_sscg_pll_ops = {
  397. .prepare = clk_sscg_pll_prepare,
  398. .unprepare = clk_sscg_pll_unprepare,
  399. .is_prepared = clk_sscg_pll_is_prepared,
  400. .recalc_rate = clk_sscg_pll_recalc_rate,
  401. .set_rate = clk_sscg_pll_set_rate,
  402. .set_parent = clk_sscg_pll_set_parent,
  403. .get_parent = clk_sscg_pll_get_parent,
  404. .determine_rate = clk_sscg_pll_determine_rate,
  405. };
  406. struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
  407. const char * const *parent_names,
  408. u8 num_parents,
  409. u8 parent, u8 bypass1, u8 bypass2,
  410. void __iomem *base,
  411. unsigned long flags)
  412. {
  413. struct clk_sscg_pll *pll;
  414. struct clk_init_data init;
  415. struct clk_hw *hw;
  416. int ret;
  417. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  418. if (!pll)
  419. return ERR_PTR(-ENOMEM);
  420. pll->parent = parent;
  421. pll->bypass1 = bypass1;
  422. pll->bypass2 = bypass2;
  423. pll->base = base;
  424. init.name = name;
  425. init.ops = &clk_sscg_pll_ops;
  426. init.flags = flags;
  427. init.parent_names = parent_names;
  428. init.num_parents = num_parents;
  429. pll->base = base;
  430. pll->hw.init = &init;
  431. hw = &pll->hw;
  432. ret = clk_hw_register(NULL, hw);
  433. if (ret) {
  434. kfree(pll);
  435. return ERR_PTR(ret);
  436. }
  437. return hw;
  438. }
  439. EXPORT_SYMBOL_GPL(imx_clk_hw_sscg_pll);