clk-pllv4.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017~2018 NXP
  5. *
  6. * Author: Dong Aisheng <aisheng.dong@nxp.com>
  7. *
  8. */
  9. #include <linux/bits.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/slab.h>
  15. #include "clk.h"
  16. /* PLL Control Status Register (xPLLCSR) */
  17. #define PLL_CSR_OFFSET 0x0
  18. #define PLL_VLD BIT(24)
  19. #define PLL_EN BIT(0)
  20. /* PLL Configuration Register (xPLLCFG) */
  21. #define PLL_CFG_OFFSET 0x08
  22. #define BP_PLL_MULT 16
  23. #define BM_PLL_MULT (0x7f << 16)
  24. /* PLL Numerator Register (xPLLNUM) */
  25. #define PLL_NUM_OFFSET 0x10
  26. /* PLL Denominator Register (xPLLDENOM) */
  27. #define PLL_DENOM_OFFSET 0x14
  28. #define MAX_MFD 0x3fffffff
  29. #define DEFAULT_MFD 1000000
  30. struct clk_pllv4 {
  31. struct clk_hw hw;
  32. void __iomem *base;
  33. };
  34. /* Valid PLL MULT Table */
  35. static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
  36. #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
  37. #define LOCK_TIMEOUT_US USEC_PER_MSEC
  38. static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
  39. {
  40. u32 csr;
  41. return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
  42. csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
  43. }
  44. static int clk_pllv4_is_prepared(struct clk_hw *hw)
  45. {
  46. struct clk_pllv4 *pll = to_clk_pllv4(hw);
  47. if (readl_relaxed(pll->base) & PLL_EN)
  48. return 1;
  49. return 0;
  50. }
  51. static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
  52. unsigned long parent_rate)
  53. {
  54. struct clk_pllv4 *pll = to_clk_pllv4(hw);
  55. u32 mult, mfn, mfd;
  56. u64 temp64;
  57. mult = readl_relaxed(pll->base + PLL_CFG_OFFSET);
  58. mult &= BM_PLL_MULT;
  59. mult >>= BP_PLL_MULT;
  60. mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
  61. mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
  62. temp64 = parent_rate;
  63. temp64 *= mfn;
  64. do_div(temp64, mfd);
  65. return (parent_rate * mult) + (u32)temp64;
  66. }
  67. static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
  68. unsigned long *prate)
  69. {
  70. unsigned long parent_rate = *prate;
  71. unsigned long round_rate, i;
  72. u32 mfn, mfd = DEFAULT_MFD;
  73. bool found = false;
  74. u64 temp64;
  75. for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
  76. round_rate = parent_rate * pllv4_mult_table[i];
  77. if (rate >= round_rate) {
  78. found = true;
  79. break;
  80. }
  81. }
  82. if (!found) {
  83. pr_warn("%s: unable to round rate %lu, parent rate %lu\n",
  84. clk_hw_get_name(hw), rate, parent_rate);
  85. return 0;
  86. }
  87. if (parent_rate <= MAX_MFD)
  88. mfd = parent_rate;
  89. temp64 = (u64)(rate - round_rate);
  90. temp64 *= mfd;
  91. do_div(temp64, parent_rate);
  92. mfn = temp64;
  93. /*
  94. * NOTE: The value of numerator must always be configured to be
  95. * less than the value of the denominator. If we can't get a proper
  96. * pair of mfn/mfd, we simply return the round_rate without using
  97. * the frac part.
  98. */
  99. if (mfn >= mfd)
  100. return round_rate;
  101. temp64 = (u64)parent_rate;
  102. temp64 *= mfn;
  103. do_div(temp64, mfd);
  104. return round_rate + (u32)temp64;
  105. }
  106. static bool clk_pllv4_is_valid_mult(unsigned int mult)
  107. {
  108. int i;
  109. /* check if mult is in valid MULT table */
  110. for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
  111. if (pllv4_mult_table[i] == mult)
  112. return true;
  113. }
  114. return false;
  115. }
  116. static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
  117. unsigned long parent_rate)
  118. {
  119. struct clk_pllv4 *pll = to_clk_pllv4(hw);
  120. u32 val, mult, mfn, mfd = DEFAULT_MFD;
  121. u64 temp64;
  122. mult = rate / parent_rate;
  123. if (!clk_pllv4_is_valid_mult(mult))
  124. return -EINVAL;
  125. if (parent_rate <= MAX_MFD)
  126. mfd = parent_rate;
  127. temp64 = (u64)(rate - mult * parent_rate);
  128. temp64 *= mfd;
  129. do_div(temp64, parent_rate);
  130. mfn = temp64;
  131. val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
  132. val &= ~BM_PLL_MULT;
  133. val |= mult << BP_PLL_MULT;
  134. writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
  135. writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
  136. writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
  137. return 0;
  138. }
  139. static int clk_pllv4_prepare(struct clk_hw *hw)
  140. {
  141. u32 val;
  142. struct clk_pllv4 *pll = to_clk_pllv4(hw);
  143. val = readl_relaxed(pll->base);
  144. val |= PLL_EN;
  145. writel_relaxed(val, pll->base);
  146. return clk_pllv4_wait_lock(pll);
  147. }
  148. static void clk_pllv4_unprepare(struct clk_hw *hw)
  149. {
  150. u32 val;
  151. struct clk_pllv4 *pll = to_clk_pllv4(hw);
  152. val = readl_relaxed(pll->base);
  153. val &= ~PLL_EN;
  154. writel_relaxed(val, pll->base);
  155. }
  156. static const struct clk_ops clk_pllv4_ops = {
  157. .recalc_rate = clk_pllv4_recalc_rate,
  158. .round_rate = clk_pllv4_round_rate,
  159. .set_rate = clk_pllv4_set_rate,
  160. .prepare = clk_pllv4_prepare,
  161. .unprepare = clk_pllv4_unprepare,
  162. .is_prepared = clk_pllv4_is_prepared,
  163. };
  164. struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
  165. void __iomem *base)
  166. {
  167. struct clk_pllv4 *pll;
  168. struct clk_hw *hw;
  169. struct clk_init_data init;
  170. int ret;
  171. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  172. if (!pll)
  173. return ERR_PTR(-ENOMEM);
  174. pll->base = base;
  175. init.name = name;
  176. init.ops = &clk_pllv4_ops;
  177. init.parent_names = &parent_name;
  178. init.num_parents = 1;
  179. init.flags = CLK_SET_RATE_GATE;
  180. pll->hw.init = &init;
  181. hw = &pll->hw;
  182. ret = clk_hw_register(NULL, hw);
  183. if (ret) {
  184. kfree(pll);
  185. hw = ERR_PTR(ret);
  186. }
  187. return hw;
  188. }