clk-pllv2.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/kernel.h>
  3. #include <linux/clk.h>
  4. #include <linux/io.h>
  5. #include <linux/errno.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/err.h>
  9. #include <asm/div64.h>
  10. #include "clk.h"
  11. #define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
  12. /* PLL Register Offsets */
  13. #define MXC_PLL_DP_CTL 0x00
  14. #define MXC_PLL_DP_CONFIG 0x04
  15. #define MXC_PLL_DP_OP 0x08
  16. #define MXC_PLL_DP_MFD 0x0C
  17. #define MXC_PLL_DP_MFN 0x10
  18. #define MXC_PLL_DP_MFNMINUS 0x14
  19. #define MXC_PLL_DP_MFNPLUS 0x18
  20. #define MXC_PLL_DP_HFS_OP 0x1C
  21. #define MXC_PLL_DP_HFS_MFD 0x20
  22. #define MXC_PLL_DP_HFS_MFN 0x24
  23. #define MXC_PLL_DP_MFN_TOGC 0x28
  24. #define MXC_PLL_DP_DESTAT 0x2c
  25. /* PLL Register Bit definitions */
  26. #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
  27. #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
  28. #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
  29. #define MXC_PLL_DP_CTL_ADE 0x800
  30. #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
  31. #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
  32. #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
  33. #define MXC_PLL_DP_CTL_HFSM 0x80
  34. #define MXC_PLL_DP_CTL_PRE 0x40
  35. #define MXC_PLL_DP_CTL_UPEN 0x20
  36. #define MXC_PLL_DP_CTL_RST 0x10
  37. #define MXC_PLL_DP_CTL_RCP 0x8
  38. #define MXC_PLL_DP_CTL_PLM 0x4
  39. #define MXC_PLL_DP_CTL_BRM0 0x2
  40. #define MXC_PLL_DP_CTL_LRF 0x1
  41. #define MXC_PLL_DP_CONFIG_BIST 0x8
  42. #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
  43. #define MXC_PLL_DP_CONFIG_AREN 0x2
  44. #define MXC_PLL_DP_CONFIG_LDREQ 0x1
  45. #define MXC_PLL_DP_OP_MFI_OFFSET 4
  46. #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
  47. #define MXC_PLL_DP_OP_PDF_OFFSET 0
  48. #define MXC_PLL_DP_OP_PDF_MASK 0xF
  49. #define MXC_PLL_DP_MFD_OFFSET 0
  50. #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
  51. #define MXC_PLL_DP_MFN_OFFSET 0x0
  52. #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
  53. #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
  54. #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
  55. #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
  56. #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
  57. #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
  58. #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
  59. #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
  60. struct clk_pllv2 {
  61. struct clk_hw hw;
  62. void __iomem *base;
  63. };
  64. static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
  65. u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
  66. {
  67. long mfi, mfn, mfd, pdf, ref_clk;
  68. unsigned long dbl;
  69. u64 temp;
  70. dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
  71. pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
  72. mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
  73. mfi = (mfi <= 5) ? 5 : mfi;
  74. mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
  75. mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
  76. mfn = sign_extend32(mfn, 26);
  77. ref_clk = 2 * parent_rate;
  78. if (dbl != 0)
  79. ref_clk *= 2;
  80. ref_clk /= (pdf + 1);
  81. temp = (u64) ref_clk * abs(mfn);
  82. do_div(temp, mfd + 1);
  83. if (mfn < 0)
  84. temp = (ref_clk * mfi) - temp;
  85. else
  86. temp = (ref_clk * mfi) + temp;
  87. return temp;
  88. }
  89. static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
  90. unsigned long parent_rate)
  91. {
  92. u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
  93. void __iomem *pllbase;
  94. struct clk_pllv2 *pll = to_clk_pllv2(hw);
  95. pllbase = pll->base;
  96. dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
  97. dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
  98. dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
  99. dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
  100. return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
  101. }
  102. static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
  103. u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
  104. {
  105. u32 reg;
  106. long mfi, pdf, mfn, mfd = 999999;
  107. u64 temp64;
  108. unsigned long quad_parent_rate;
  109. quad_parent_rate = 4 * parent_rate;
  110. pdf = mfi = -1;
  111. while (++pdf < 16 && mfi < 5)
  112. mfi = rate * (pdf+1) / quad_parent_rate;
  113. if (mfi > 15)
  114. return -EINVAL;
  115. pdf--;
  116. temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
  117. do_div(temp64, quad_parent_rate / 1000000);
  118. mfn = (long)temp64;
  119. reg = mfi << 4 | pdf;
  120. *dp_op = reg;
  121. *dp_mfd = mfd;
  122. *dp_mfn = mfn;
  123. return 0;
  124. }
  125. static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
  126. unsigned long parent_rate)
  127. {
  128. struct clk_pllv2 *pll = to_clk_pllv2(hw);
  129. void __iomem *pllbase;
  130. u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
  131. int ret;
  132. pllbase = pll->base;
  133. ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
  134. if (ret)
  135. return ret;
  136. dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
  137. /* use dpdck0_2 */
  138. __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
  139. __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
  140. __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
  141. __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
  142. return 0;
  143. }
  144. static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
  145. unsigned long *prate)
  146. {
  147. u32 dp_op, dp_mfd, dp_mfn;
  148. int ret;
  149. ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
  150. if (ret)
  151. return ret;
  152. return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
  153. dp_op, dp_mfd, dp_mfn);
  154. }
  155. static int clk_pllv2_prepare(struct clk_hw *hw)
  156. {
  157. struct clk_pllv2 *pll = to_clk_pllv2(hw);
  158. u32 reg;
  159. void __iomem *pllbase;
  160. int i = 0;
  161. pllbase = pll->base;
  162. reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
  163. __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
  164. /* Wait for lock */
  165. do {
  166. reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
  167. if (reg & MXC_PLL_DP_CTL_LRF)
  168. break;
  169. udelay(1);
  170. } while (++i < MAX_DPLL_WAIT_TRIES);
  171. if (i == MAX_DPLL_WAIT_TRIES) {
  172. pr_err("MX5: pll locking failed\n");
  173. return -EINVAL;
  174. }
  175. return 0;
  176. }
  177. static void clk_pllv2_unprepare(struct clk_hw *hw)
  178. {
  179. struct clk_pllv2 *pll = to_clk_pllv2(hw);
  180. u32 reg;
  181. void __iomem *pllbase;
  182. pllbase = pll->base;
  183. reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
  184. __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
  185. }
  186. static const struct clk_ops clk_pllv2_ops = {
  187. .prepare = clk_pllv2_prepare,
  188. .unprepare = clk_pllv2_unprepare,
  189. .recalc_rate = clk_pllv2_recalc_rate,
  190. .round_rate = clk_pllv2_round_rate,
  191. .set_rate = clk_pllv2_set_rate,
  192. };
  193. struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
  194. void __iomem *base)
  195. {
  196. struct clk_pllv2 *pll;
  197. struct clk_hw *hw;
  198. struct clk_init_data init;
  199. int ret;
  200. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  201. if (!pll)
  202. return ERR_PTR(-ENOMEM);
  203. pll->base = base;
  204. init.name = name;
  205. init.ops = &clk_pllv2_ops;
  206. init.flags = 0;
  207. init.parent_names = &parent;
  208. init.num_parents = 1;
  209. pll->hw.init = &init;
  210. hw = &pll->hw;
  211. ret = clk_hw_register(NULL, hw);
  212. if (ret) {
  213. kfree(pll);
  214. return ERR_PTR(ret);
  215. }
  216. return hw;
  217. }