clk-pllv1.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/bits.h>
  3. #include <linux/clk-provider.h>
  4. #include <linux/io.h>
  5. #include <linux/slab.h>
  6. #include <linux/kernel.h>
  7. #include <linux/err.h>
  8. #include "clk.h"
  9. /**
  10. * pll v1
  11. *
  12. * @clk_hw clock source
  13. * @parent the parent clock name
  14. * @base base address of pll registers
  15. *
  16. * PLL clock version 1, found on i.MX1/21/25/27/31/35
  17. */
  18. #define MFN_BITS (10)
  19. #define MFN_SIGN (BIT(MFN_BITS - 1))
  20. #define MFN_MASK (MFN_SIGN - 1)
  21. struct clk_pllv1 {
  22. struct clk_hw hw;
  23. void __iomem *base;
  24. enum imx_pllv1_type type;
  25. };
  26. #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
  27. static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)
  28. {
  29. return pll->type == IMX_PLLV1_IMX1;
  30. }
  31. static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)
  32. {
  33. return pll->type == IMX_PLLV1_IMX21;
  34. }
  35. static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)
  36. {
  37. return pll->type == IMX_PLLV1_IMX27;
  38. }
  39. static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)
  40. {
  41. return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);
  42. }
  43. static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
  44. unsigned long parent_rate)
  45. {
  46. struct clk_pllv1 *pll = to_clk_pllv1(hw);
  47. unsigned long long ull;
  48. int mfn_abs;
  49. unsigned int mfi, mfn, mfd, pd;
  50. u32 reg;
  51. unsigned long rate;
  52. reg = readl(pll->base);
  53. /*
  54. * Get the resulting clock rate from a PLL register value and the input
  55. * frequency. PLLs with this register layout can be found on i.MX1,
  56. * i.MX21, i.MX27 and i,MX31
  57. *
  58. * mfi + mfn / (mfd + 1)
  59. * f = 2 * f_ref * --------------------
  60. * pd + 1
  61. */
  62. mfi = (reg >> 10) & 0xf;
  63. mfn = reg & 0x3ff;
  64. mfd = (reg >> 16) & 0x3ff;
  65. pd = (reg >> 26) & 0xf;
  66. mfi = mfi <= 5 ? 5 : mfi;
  67. mfn_abs = mfn;
  68. /*
  69. * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
  70. * 2's complements number.
  71. * On i.MX27 the bit 9 is the sign bit.
  72. */
  73. if (mfn_is_negative(pll, mfn)) {
  74. if (is_imx27_pllv1(pll))
  75. mfn_abs = mfn & MFN_MASK;
  76. else
  77. mfn_abs = BIT(MFN_BITS) - mfn;
  78. }
  79. rate = parent_rate * 2;
  80. rate /= pd + 1;
  81. ull = (unsigned long long)rate * mfn_abs;
  82. do_div(ull, mfd + 1);
  83. if (mfn_is_negative(pll, mfn))
  84. ull = (rate * mfi) - ull;
  85. else
  86. ull = (rate * mfi) + ull;
  87. return ull;
  88. }
  89. static const struct clk_ops clk_pllv1_ops = {
  90. .recalc_rate = clk_pllv1_recalc_rate,
  91. };
  92. struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
  93. const char *parent, void __iomem *base)
  94. {
  95. struct clk_pllv1 *pll;
  96. struct clk_hw *hw;
  97. struct clk_init_data init;
  98. int ret;
  99. pll = kmalloc(sizeof(*pll), GFP_KERNEL);
  100. if (!pll)
  101. return ERR_PTR(-ENOMEM);
  102. pll->base = base;
  103. pll->type = type;
  104. init.name = name;
  105. init.ops = &clk_pllv1_ops;
  106. init.flags = 0;
  107. init.parent_names = &parent;
  108. init.num_parents = 1;
  109. pll->hw.init = &init;
  110. hw = &pll->hw;
  111. ret = clk_hw_register(NULL, hw);
  112. if (ret) {
  113. kfree(pll);
  114. return ERR_PTR(ret);
  115. }
  116. return hw;
  117. }