clk-pll14xx.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2017-2018 NXP.
  4. */
  5. #include <linux/bits.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/export.h>
  9. #include <linux/io.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/slab.h>
  12. #include <linux/jiffies.h>
  13. #include "clk.h"
  14. #define GNRL_CTL 0x0
  15. #define DIV_CTL 0x4
  16. #define LOCK_STATUS BIT(31)
  17. #define LOCK_SEL_MASK BIT(29)
  18. #define CLKE_MASK BIT(11)
  19. #define RST_MASK BIT(9)
  20. #define BYPASS_MASK BIT(4)
  21. #define MDIV_SHIFT 12
  22. #define MDIV_MASK GENMASK(21, 12)
  23. #define PDIV_SHIFT 4
  24. #define PDIV_MASK GENMASK(9, 4)
  25. #define SDIV_SHIFT 0
  26. #define SDIV_MASK GENMASK(2, 0)
  27. #define KDIV_SHIFT 0
  28. #define KDIV_MASK GENMASK(15, 0)
  29. #define LOCK_TIMEOUT_US 10000
  30. struct clk_pll14xx {
  31. struct clk_hw hw;
  32. void __iomem *base;
  33. enum imx_pll14xx_type type;
  34. const struct imx_pll14xx_rate_table *rate_table;
  35. int rate_count;
  36. };
  37. #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
  38. static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
  39. PLL_1416X_RATE(1800000000U, 225, 3, 0),
  40. PLL_1416X_RATE(1600000000U, 200, 3, 0),
  41. PLL_1416X_RATE(1500000000U, 375, 3, 1),
  42. PLL_1416X_RATE(1400000000U, 350, 3, 1),
  43. PLL_1416X_RATE(1200000000U, 300, 3, 1),
  44. PLL_1416X_RATE(1000000000U, 250, 3, 1),
  45. PLL_1416X_RATE(800000000U, 200, 3, 1),
  46. PLL_1416X_RATE(750000000U, 250, 2, 2),
  47. PLL_1416X_RATE(700000000U, 350, 3, 2),
  48. PLL_1416X_RATE(600000000U, 300, 3, 2),
  49. };
  50. static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
  51. PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
  52. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  53. PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
  54. PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
  55. PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
  56. PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
  57. };
  58. struct imx_pll14xx_clk imx_1443x_pll = {
  59. .type = PLL_1443X,
  60. .rate_table = imx_pll1443x_tbl,
  61. .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
  62. };
  63. EXPORT_SYMBOL_GPL(imx_1443x_pll);
  64. struct imx_pll14xx_clk imx_1443x_dram_pll = {
  65. .type = PLL_1443X,
  66. .rate_table = imx_pll1443x_tbl,
  67. .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
  68. .flags = CLK_GET_RATE_NOCACHE,
  69. };
  70. EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
  71. struct imx_pll14xx_clk imx_1416x_pll = {
  72. .type = PLL_1416X,
  73. .rate_table = imx_pll1416x_tbl,
  74. .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
  75. };
  76. EXPORT_SYMBOL_GPL(imx_1416x_pll);
  77. static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
  78. struct clk_pll14xx *pll, unsigned long rate)
  79. {
  80. const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  81. int i;
  82. for (i = 0; i < pll->rate_count; i++)
  83. if (rate == rate_table[i].rate)
  84. return &rate_table[i];
  85. return NULL;
  86. }
  87. static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
  88. unsigned long *prate)
  89. {
  90. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  91. const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  92. int i;
  93. /* Assumming rate_table is in descending order */
  94. for (i = 0; i < pll->rate_count; i++)
  95. if (rate >= rate_table[i].rate)
  96. return rate_table[i].rate;
  97. /* return minimum supported value */
  98. return rate_table[i - 1].rate;
  99. }
  100. static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
  101. unsigned long parent_rate)
  102. {
  103. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  104. u32 mdiv, pdiv, sdiv, pll_div;
  105. u64 fvco = parent_rate;
  106. pll_div = readl_relaxed(pll->base + 4);
  107. mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  108. pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  109. sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
  110. fvco *= mdiv;
  111. do_div(fvco, pdiv << sdiv);
  112. return fvco;
  113. }
  114. static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
  115. unsigned long parent_rate)
  116. {
  117. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  118. u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
  119. short int kdiv;
  120. u64 fvco = parent_rate;
  121. pll_div_ctl0 = readl_relaxed(pll->base + 4);
  122. pll_div_ctl1 = readl_relaxed(pll->base + 8);
  123. mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  124. pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  125. sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
  126. kdiv = pll_div_ctl1 & KDIV_MASK;
  127. /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
  128. fvco *= (mdiv * 65536 + kdiv);
  129. pdiv *= 65536;
  130. do_div(fvco, pdiv << sdiv);
  131. return fvco;
  132. }
  133. static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
  134. u32 pll_div)
  135. {
  136. u32 old_mdiv, old_pdiv;
  137. old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  138. old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  139. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
  140. }
  141. static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
  142. {
  143. u32 val;
  144. return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,
  145. LOCK_TIMEOUT_US);
  146. }
  147. static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
  148. unsigned long prate)
  149. {
  150. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  151. const struct imx_pll14xx_rate_table *rate;
  152. u32 tmp, div_val;
  153. int ret;
  154. rate = imx_get_pll_settings(pll, drate);
  155. if (!rate) {
  156. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  157. drate, clk_hw_get_name(hw));
  158. return -EINVAL;
  159. }
  160. tmp = readl_relaxed(pll->base + 4);
  161. if (!clk_pll14xx_mp_change(rate, tmp)) {
  162. tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
  163. tmp |= rate->sdiv << SDIV_SHIFT;
  164. writel_relaxed(tmp, pll->base + 4);
  165. return 0;
  166. }
  167. /* Bypass clock and set lock to pll output lock */
  168. tmp = readl_relaxed(pll->base);
  169. tmp |= LOCK_SEL_MASK;
  170. writel_relaxed(tmp, pll->base);
  171. /* Enable RST */
  172. tmp &= ~RST_MASK;
  173. writel_relaxed(tmp, pll->base);
  174. /* Enable BYPASS */
  175. tmp |= BYPASS_MASK;
  176. writel(tmp, pll->base);
  177. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  178. (rate->sdiv << SDIV_SHIFT);
  179. writel_relaxed(div_val, pll->base + 0x4);
  180. /*
  181. * According to SPEC, t3 - t2 need to be greater than
  182. * 1us and 1/FREF, respectively.
  183. * FREF is FIN / Prediv, the prediv is [1, 63], so choose
  184. * 3us.
  185. */
  186. udelay(3);
  187. /* Disable RST */
  188. tmp |= RST_MASK;
  189. writel_relaxed(tmp, pll->base);
  190. /* Wait Lock */
  191. ret = clk_pll14xx_wait_lock(pll);
  192. if (ret)
  193. return ret;
  194. /* Bypass */
  195. tmp &= ~BYPASS_MASK;
  196. writel_relaxed(tmp, pll->base);
  197. return 0;
  198. }
  199. static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
  200. unsigned long prate)
  201. {
  202. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  203. const struct imx_pll14xx_rate_table *rate;
  204. u32 tmp, div_val;
  205. int ret;
  206. rate = imx_get_pll_settings(pll, drate);
  207. if (!rate) {
  208. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  209. drate, clk_hw_get_name(hw));
  210. return -EINVAL;
  211. }
  212. tmp = readl_relaxed(pll->base + 4);
  213. if (!clk_pll14xx_mp_change(rate, tmp)) {
  214. tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
  215. tmp |= rate->sdiv << SDIV_SHIFT;
  216. writel_relaxed(tmp, pll->base + 4);
  217. tmp = rate->kdiv << KDIV_SHIFT;
  218. writel_relaxed(tmp, pll->base + 8);
  219. return 0;
  220. }
  221. /* Enable RST */
  222. tmp = readl_relaxed(pll->base);
  223. tmp &= ~RST_MASK;
  224. writel_relaxed(tmp, pll->base);
  225. /* Enable BYPASS */
  226. tmp |= BYPASS_MASK;
  227. writel_relaxed(tmp, pll->base);
  228. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  229. (rate->sdiv << SDIV_SHIFT);
  230. writel_relaxed(div_val, pll->base + 0x4);
  231. writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
  232. /*
  233. * According to SPEC, t3 - t2 need to be greater than
  234. * 1us and 1/FREF, respectively.
  235. * FREF is FIN / Prediv, the prediv is [1, 63], so choose
  236. * 3us.
  237. */
  238. udelay(3);
  239. /* Disable RST */
  240. tmp |= RST_MASK;
  241. writel_relaxed(tmp, pll->base);
  242. /* Wait Lock*/
  243. ret = clk_pll14xx_wait_lock(pll);
  244. if (ret)
  245. return ret;
  246. /* Bypass */
  247. tmp &= ~BYPASS_MASK;
  248. writel_relaxed(tmp, pll->base);
  249. return 0;
  250. }
  251. static int clk_pll14xx_prepare(struct clk_hw *hw)
  252. {
  253. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  254. u32 val;
  255. int ret;
  256. /*
  257. * RESETB = 1 from 0, PLL starts its normal
  258. * operation after lock time
  259. */
  260. val = readl_relaxed(pll->base + GNRL_CTL);
  261. if (val & RST_MASK)
  262. return 0;
  263. val |= BYPASS_MASK;
  264. writel_relaxed(val, pll->base + GNRL_CTL);
  265. val |= RST_MASK;
  266. writel_relaxed(val, pll->base + GNRL_CTL);
  267. ret = clk_pll14xx_wait_lock(pll);
  268. if (ret)
  269. return ret;
  270. val &= ~BYPASS_MASK;
  271. writel_relaxed(val, pll->base + GNRL_CTL);
  272. return 0;
  273. }
  274. static int clk_pll14xx_is_prepared(struct clk_hw *hw)
  275. {
  276. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  277. u32 val;
  278. val = readl_relaxed(pll->base + GNRL_CTL);
  279. return (val & RST_MASK) ? 1 : 0;
  280. }
  281. static void clk_pll14xx_unprepare(struct clk_hw *hw)
  282. {
  283. struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  284. u32 val;
  285. /*
  286. * Set RST to 0, power down mode is enabled and
  287. * every digital block is reset
  288. */
  289. val = readl_relaxed(pll->base + GNRL_CTL);
  290. val &= ~RST_MASK;
  291. writel_relaxed(val, pll->base + GNRL_CTL);
  292. }
  293. static const struct clk_ops clk_pll1416x_ops = {
  294. .prepare = clk_pll14xx_prepare,
  295. .unprepare = clk_pll14xx_unprepare,
  296. .is_prepared = clk_pll14xx_is_prepared,
  297. .recalc_rate = clk_pll1416x_recalc_rate,
  298. .round_rate = clk_pll14xx_round_rate,
  299. .set_rate = clk_pll1416x_set_rate,
  300. };
  301. static const struct clk_ops clk_pll1416x_min_ops = {
  302. .recalc_rate = clk_pll1416x_recalc_rate,
  303. };
  304. static const struct clk_ops clk_pll1443x_ops = {
  305. .prepare = clk_pll14xx_prepare,
  306. .unprepare = clk_pll14xx_unprepare,
  307. .is_prepared = clk_pll14xx_is_prepared,
  308. .recalc_rate = clk_pll1443x_recalc_rate,
  309. .round_rate = clk_pll14xx_round_rate,
  310. .set_rate = clk_pll1443x_set_rate,
  311. };
  312. struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
  313. const char *parent_name, void __iomem *base,
  314. const struct imx_pll14xx_clk *pll_clk)
  315. {
  316. struct clk_pll14xx *pll;
  317. struct clk_hw *hw;
  318. struct clk_init_data init;
  319. int ret;
  320. u32 val;
  321. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  322. if (!pll)
  323. return ERR_PTR(-ENOMEM);
  324. init.name = name;
  325. init.flags = pll_clk->flags;
  326. init.parent_names = &parent_name;
  327. init.num_parents = 1;
  328. switch (pll_clk->type) {
  329. case PLL_1416X:
  330. if (!pll_clk->rate_table)
  331. init.ops = &clk_pll1416x_min_ops;
  332. else
  333. init.ops = &clk_pll1416x_ops;
  334. break;
  335. case PLL_1443X:
  336. init.ops = &clk_pll1443x_ops;
  337. break;
  338. default:
  339. pr_err("%s: Unknown pll type for pll clk %s\n",
  340. __func__, name);
  341. kfree(pll);
  342. return ERR_PTR(-EINVAL);
  343. };
  344. pll->base = base;
  345. pll->hw.init = &init;
  346. pll->type = pll_clk->type;
  347. pll->rate_table = pll_clk->rate_table;
  348. pll->rate_count = pll_clk->rate_count;
  349. val = readl_relaxed(pll->base + GNRL_CTL);
  350. val &= ~BYPASS_MASK;
  351. writel_relaxed(val, pll->base + GNRL_CTL);
  352. hw = &pll->hw;
  353. ret = clk_hw_register(dev, hw);
  354. if (ret) {
  355. pr_err("%s: failed to register pll %s %d\n",
  356. __func__, name, ret);
  357. kfree(pll);
  358. return ERR_PTR(ret);
  359. }
  360. return hw;
  361. }
  362. EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx);