clk-pfdv2.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017~2018 NXP
  5. *
  6. * Author: Dong Aisheng <aisheng.dong@nxp.com>
  7. *
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/slab.h>
  14. #include "clk.h"
  15. /**
  16. * struct clk_pfdv2 - IMX PFD clock
  17. * @hw: clock source
  18. * @reg: PFD register address
  19. * @gate_bit: Gate bit offset
  20. * @vld_bit: Valid bit offset
  21. * @frac_off: PLL Fractional Divider offset
  22. */
  23. struct clk_pfdv2 {
  24. struct clk_hw hw;
  25. void __iomem *reg;
  26. u8 gate_bit;
  27. u8 vld_bit;
  28. u8 frac_off;
  29. };
  30. #define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
  31. #define CLK_PFDV2_FRAC_MASK 0x3f
  32. #define LOCK_TIMEOUT_US USEC_PER_MSEC
  33. static DEFINE_SPINLOCK(pfd_lock);
  34. static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
  35. {
  36. u32 val;
  37. return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),
  38. 0, LOCK_TIMEOUT_US);
  39. }
  40. static int clk_pfdv2_enable(struct clk_hw *hw)
  41. {
  42. struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
  43. unsigned long flags;
  44. u32 val;
  45. spin_lock_irqsave(&pfd_lock, flags);
  46. val = readl_relaxed(pfd->reg);
  47. val &= ~(1 << pfd->gate_bit);
  48. writel_relaxed(val, pfd->reg);
  49. spin_unlock_irqrestore(&pfd_lock, flags);
  50. return clk_pfdv2_wait(pfd);
  51. }
  52. static void clk_pfdv2_disable(struct clk_hw *hw)
  53. {
  54. struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
  55. unsigned long flags;
  56. u32 val;
  57. spin_lock_irqsave(&pfd_lock, flags);
  58. val = readl_relaxed(pfd->reg);
  59. val |= (1 << pfd->gate_bit);
  60. writel_relaxed(val, pfd->reg);
  61. spin_unlock_irqrestore(&pfd_lock, flags);
  62. }
  63. static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
  64. unsigned long parent_rate)
  65. {
  66. struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
  67. u64 tmp = parent_rate;
  68. u8 frac;
  69. frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
  70. & CLK_PFDV2_FRAC_MASK;
  71. if (!frac) {
  72. pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
  73. clk_hw_get_name(hw));
  74. return 0;
  75. }
  76. tmp *= 18;
  77. do_div(tmp, frac);
  78. return tmp;
  79. }
  80. static int clk_pfdv2_determine_rate(struct clk_hw *hw,
  81. struct clk_rate_request *req)
  82. {
  83. unsigned long parent_rates[] = {
  84. 480000000,
  85. 528000000,
  86. req->best_parent_rate
  87. };
  88. unsigned long best_rate = -1UL, rate = req->rate;
  89. unsigned long best_parent_rate = req->best_parent_rate;
  90. u64 tmp;
  91. u8 frac;
  92. int i;
  93. for (i = 0; i < ARRAY_SIZE(parent_rates); i++) {
  94. tmp = parent_rates[i];
  95. tmp = tmp * 18 + rate / 2;
  96. do_div(tmp, rate);
  97. frac = tmp;
  98. if (frac < 12)
  99. frac = 12;
  100. else if (frac > 35)
  101. frac = 35;
  102. tmp = parent_rates[i];
  103. tmp *= 18;
  104. do_div(tmp, frac);
  105. if (abs(tmp - req->rate) < abs(best_rate - req->rate)) {
  106. best_rate = tmp;
  107. best_parent_rate = parent_rates[i];
  108. }
  109. }
  110. req->best_parent_rate = best_parent_rate;
  111. req->rate = best_rate;
  112. return 0;
  113. }
  114. static int clk_pfdv2_is_enabled(struct clk_hw *hw)
  115. {
  116. struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
  117. if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))
  118. return 0;
  119. return 1;
  120. }
  121. static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
  122. unsigned long parent_rate)
  123. {
  124. struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
  125. unsigned long flags;
  126. u64 tmp = parent_rate;
  127. u32 val;
  128. u8 frac;
  129. if (!rate)
  130. return -EINVAL;
  131. /* PFD can NOT change rate without gating */
  132. WARN_ON(clk_pfdv2_is_enabled(hw));
  133. tmp = tmp * 18 + rate / 2;
  134. do_div(tmp, rate);
  135. frac = tmp;
  136. if (frac < 12)
  137. frac = 12;
  138. else if (frac > 35)
  139. frac = 35;
  140. spin_lock_irqsave(&pfd_lock, flags);
  141. val = readl_relaxed(pfd->reg);
  142. val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off);
  143. val |= frac << pfd->frac_off;
  144. writel_relaxed(val, pfd->reg);
  145. spin_unlock_irqrestore(&pfd_lock, flags);
  146. return 0;
  147. }
  148. static const struct clk_ops clk_pfdv2_ops = {
  149. .enable = clk_pfdv2_enable,
  150. .disable = clk_pfdv2_disable,
  151. .recalc_rate = clk_pfdv2_recalc_rate,
  152. .determine_rate = clk_pfdv2_determine_rate,
  153. .set_rate = clk_pfdv2_set_rate,
  154. .is_enabled = clk_pfdv2_is_enabled,
  155. };
  156. struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
  157. void __iomem *reg, u8 idx)
  158. {
  159. struct clk_init_data init;
  160. struct clk_pfdv2 *pfd;
  161. struct clk_hw *hw;
  162. int ret;
  163. WARN_ON(idx > 3);
  164. pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
  165. if (!pfd)
  166. return ERR_PTR(-ENOMEM);
  167. pfd->reg = reg;
  168. pfd->gate_bit = (idx + 1) * 8 - 1;
  169. pfd->vld_bit = pfd->gate_bit - 1;
  170. pfd->frac_off = idx * 8;
  171. init.name = name;
  172. init.ops = &clk_pfdv2_ops;
  173. init.parent_names = &parent_name;
  174. init.num_parents = 1;
  175. init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
  176. pfd->hw.init = &init;
  177. hw = &pfd->hw;
  178. ret = clk_hw_register(NULL, hw);
  179. if (ret) {
  180. kfree(pfd);
  181. hw = ERR_PTR(ret);
  182. }
  183. return hw;
  184. }