clk-lpcg-scu.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. * Dong Aisheng <aisheng.dong@nxp.com>
  5. */
  6. #include <linux/bits.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/slab.h>
  11. #include <linux/spinlock.h>
  12. #include "clk-scu.h"
  13. static DEFINE_SPINLOCK(imx_lpcg_scu_lock);
  14. #define CLK_GATE_SCU_LPCG_MASK 0x3
  15. #define CLK_GATE_SCU_LPCG_HW_SEL BIT(0)
  16. #define CLK_GATE_SCU_LPCG_SW_SEL BIT(1)
  17. /*
  18. * struct clk_lpcg_scu - Description of LPCG clock
  19. *
  20. * @hw: clk_hw of this LPCG
  21. * @reg: register of this LPCG clock
  22. * @bit_idx: bit index of this LPCG clock
  23. * @hw_gate: HW auto gate enable
  24. *
  25. * This structure describes one LPCG clock
  26. */
  27. struct clk_lpcg_scu {
  28. struct clk_hw hw;
  29. void __iomem *reg;
  30. u8 bit_idx;
  31. bool hw_gate;
  32. };
  33. #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
  34. static int clk_lpcg_scu_enable(struct clk_hw *hw)
  35. {
  36. struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
  37. unsigned long flags;
  38. u32 reg, val;
  39. spin_lock_irqsave(&imx_lpcg_scu_lock, flags);
  40. reg = readl_relaxed(clk->reg);
  41. reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
  42. val = CLK_GATE_SCU_LPCG_SW_SEL;
  43. if (clk->hw_gate)
  44. val |= CLK_GATE_SCU_LPCG_HW_SEL;
  45. reg |= val << clk->bit_idx;
  46. writel(reg, clk->reg);
  47. spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
  48. return 0;
  49. }
  50. static void clk_lpcg_scu_disable(struct clk_hw *hw)
  51. {
  52. struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
  53. unsigned long flags;
  54. u32 reg;
  55. spin_lock_irqsave(&imx_lpcg_scu_lock, flags);
  56. reg = readl_relaxed(clk->reg);
  57. reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
  58. writel(reg, clk->reg);
  59. spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
  60. }
  61. static const struct clk_ops clk_lpcg_scu_ops = {
  62. .enable = clk_lpcg_scu_enable,
  63. .disable = clk_lpcg_scu_disable,
  64. };
  65. struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
  66. unsigned long flags, void __iomem *reg,
  67. u8 bit_idx, bool hw_gate)
  68. {
  69. struct clk_lpcg_scu *clk;
  70. struct clk_init_data init;
  71. struct clk_hw *hw;
  72. int ret;
  73. clk = kzalloc(sizeof(*clk), GFP_KERNEL);
  74. if (!clk)
  75. return ERR_PTR(-ENOMEM);
  76. clk->reg = reg;
  77. clk->bit_idx = bit_idx;
  78. clk->hw_gate = hw_gate;
  79. init.name = name;
  80. init.ops = &clk_lpcg_scu_ops;
  81. init.flags = CLK_SET_RATE_PARENT | flags;
  82. init.parent_names = parent_name ? &parent_name : NULL;
  83. init.num_parents = parent_name ? 1 : 0;
  84. clk->hw.init = &init;
  85. hw = &clk->hw;
  86. ret = clk_hw_register(NULL, hw);
  87. if (ret) {
  88. kfree(clk);
  89. hw = ERR_PTR(ret);
  90. }
  91. return hw;
  92. }