clk-imx8qxp-lpcg.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. * Dong Aisheng <aisheng.dong@nxp.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include "clk-scu.h"
  15. #include "clk-imx8qxp-lpcg.h"
  16. #include <dt-bindings/clock/imx8-clock.h>
  17. /*
  18. * struct imx8qxp_lpcg_data - Description of one LPCG clock
  19. * @id: clock ID
  20. * @name: clock name
  21. * @parent: parent clock name
  22. * @flags: common clock flags
  23. * @offset: offset of this LPCG clock
  24. * @bit_idx: bit index of this LPCG clock
  25. * @hw_gate: whether supports HW autogate
  26. *
  27. * This structure describes one LPCG clock
  28. */
  29. struct imx8qxp_lpcg_data {
  30. int id;
  31. char *name;
  32. char *parent;
  33. unsigned long flags;
  34. u32 offset;
  35. u8 bit_idx;
  36. bool hw_gate;
  37. };
  38. /*
  39. * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
  40. * @lpcg: LPCG clocks array of one subsystem
  41. * @num_lpcg: the number of LPCG clocks
  42. * @num_max: the maximum number of LPCG clocks
  43. *
  44. * This structure describes each subsystem LPCG clocks information
  45. * which then will be used to create respective LPCGs clocks
  46. */
  47. struct imx8qxp_ss_lpcg {
  48. const struct imx8qxp_lpcg_data *lpcg;
  49. u8 num_lpcg;
  50. u8 num_max;
  51. };
  52. static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
  53. { IMX_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, },
  54. { IMX_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, },
  55. { IMX_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, },
  56. { IMX_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, },
  57. { IMX_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, },
  58. { IMX_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, },
  59. { IMX_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, },
  60. { IMX_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, },
  61. { IMX_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, },
  62. { IMX_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, },
  63. { IMX_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, },
  64. { IMX_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, },
  65. { IMX_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, },
  66. { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
  67. { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
  68. { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
  69. { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
  70. { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
  71. { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
  72. { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
  73. };
  74. static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
  75. .lpcg = imx8qxp_lpcg_adma,
  76. .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma),
  77. .num_max = IMX_ADMA_LPCG_CLK_END,
  78. };
  79. static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = {
  80. { IMX_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, },
  81. { IMX_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, },
  82. { IMX_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, },
  83. { IMX_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, },
  84. { IMX_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, },
  85. { IMX_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, },
  86. { IMX_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, },
  87. { IMX_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, },
  88. { IMX_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, },
  89. { IMX_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, },
  90. { IMX_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, },
  91. { IMX_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, },
  92. { IMX_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, },
  93. { IMX_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, },
  94. { IMX_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, },
  95. { IMX_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, },
  96. { IMX_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, },
  97. { IMX_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, },
  98. { IMX_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, },
  99. };
  100. static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = {
  101. .lpcg = imx8qxp_lpcg_conn,
  102. .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn),
  103. .num_max = IMX_CONN_LPCG_CLK_END,
  104. };
  105. static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
  106. { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, },
  107. { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, },
  108. { IMX_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, },
  109. { IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, },
  110. { IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, },
  111. { IMX_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, },
  112. { IMX_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, },
  113. { IMX_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, },
  114. { IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, },
  115. { IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, },
  116. { IMX_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, },
  117. { IMX_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, },
  118. { IMX_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, },
  119. { IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, },
  120. { IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, },
  121. { IMX_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, },
  122. { IMX_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, },
  123. { IMX_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, },
  124. { IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, },
  125. { IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, },
  126. { IMX_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, },
  127. { IMX_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, },
  128. { IMX_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, },
  129. { IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, },
  130. { IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, },
  131. { IMX_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, },
  132. { IMX_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, },
  133. { IMX_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, },
  134. { IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, },
  135. { IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, },
  136. { IMX_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, },
  137. { IMX_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, },
  138. { IMX_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, },
  139. { IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, },
  140. { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
  141. };
  142. static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
  143. .lpcg = imx8qxp_lpcg_lsio,
  144. .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
  145. .num_max = IMX_LSIO_LPCG_CLK_END,
  146. };
  147. static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
  148. {
  149. struct device *dev = &pdev->dev;
  150. struct device_node *np = dev->of_node;
  151. struct clk_hw_onecell_data *clk_data;
  152. const struct imx8qxp_ss_lpcg *ss_lpcg;
  153. const struct imx8qxp_lpcg_data *lpcg;
  154. struct resource *res;
  155. struct clk_hw **clks;
  156. void __iomem *base;
  157. int i;
  158. ss_lpcg = of_device_get_match_data(dev);
  159. if (!ss_lpcg)
  160. return -ENODEV;
  161. /*
  162. * Please don't replace this with devm_platform_ioremap_resource.
  163. *
  164. * devm_platform_ioremap_resource calls devm_ioremap_resource which
  165. * differs from devm_ioremap by also calling devm_request_mem_region
  166. * and preventing other mappings in the same area.
  167. *
  168. * On imx8 the LPCG nodes map entire subsystems and overlap
  169. * peripherals, this means that using devm_platform_ioremap_resource
  170. * will cause many devices to fail to probe including serial ports.
  171. */
  172. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  173. if (!res)
  174. return -EINVAL;
  175. base = devm_ioremap(dev, res->start, resource_size(res));
  176. if (!base)
  177. return -ENOMEM;
  178. clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
  179. ss_lpcg->num_max), GFP_KERNEL);
  180. if (!clk_data)
  181. return -ENOMEM;
  182. clk_data->num = ss_lpcg->num_max;
  183. clks = clk_data->hws;
  184. for (i = 0; i < ss_lpcg->num_lpcg; i++) {
  185. lpcg = ss_lpcg->lpcg + i;
  186. clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,
  187. lpcg->flags, base + lpcg->offset,
  188. lpcg->bit_idx, lpcg->hw_gate);
  189. }
  190. for (i = 0; i < clk_data->num; i++) {
  191. if (IS_ERR(clks[i]))
  192. pr_warn("i.MX clk %u: register failed with %ld\n",
  193. i, PTR_ERR(clks[i]));
  194. }
  195. return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
  196. }
  197. static const struct of_device_id imx8qxp_lpcg_match[] = {
  198. { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
  199. { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
  200. { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
  201. { /* sentinel */ }
  202. };
  203. static struct platform_driver imx8qxp_lpcg_clk_driver = {
  204. .driver = {
  205. .name = "imx8qxp-lpcg-clk",
  206. .of_match_table = imx8qxp_lpcg_match,
  207. .suppress_bind_attrs = true,
  208. },
  209. .probe = imx8qxp_lpcg_clk_probe,
  210. };
  211. module_platform_driver(imx8qxp_lpcg_clk_driver);
  212. MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
  213. MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");
  214. MODULE_LICENSE("GPL v2");