clk-gate2.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
  4. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  5. *
  6. * Gated clock implementation
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/export.h>
  10. #include <linux/module.h>
  11. #include <linux/slab.h>
  12. #include <linux/io.h>
  13. #include <linux/err.h>
  14. #include <linux/string.h>
  15. #include "clk.h"
  16. /**
  17. * DOC: basic gateable clock which can gate and ungate its output
  18. *
  19. * Traits of this clock:
  20. * prepare - clk_(un)prepare only ensures parent is (un)prepared
  21. * enable - clk_enable and clk_disable are functional & control gating
  22. * rate - inherits rate from parent. No clk_set_rate support
  23. * parent - fixed parent. No clk_set_parent support
  24. */
  25. struct clk_gate2 {
  26. struct clk_hw hw;
  27. void __iomem *reg;
  28. u8 bit_idx;
  29. u8 cgr_val;
  30. u8 flags;
  31. spinlock_t *lock;
  32. unsigned int *share_count;
  33. };
  34. #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
  35. static int clk_gate2_enable(struct clk_hw *hw)
  36. {
  37. struct clk_gate2 *gate = to_clk_gate2(hw);
  38. u32 reg;
  39. unsigned long flags;
  40. int ret = 0;
  41. spin_lock_irqsave(gate->lock, flags);
  42. if (gate->share_count && (*gate->share_count)++ > 0)
  43. goto out;
  44. if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
  45. ret = clk_gate_ops.enable(hw);
  46. } else {
  47. reg = readl(gate->reg);
  48. reg &= ~(3 << gate->bit_idx);
  49. reg |= gate->cgr_val << gate->bit_idx;
  50. writel(reg, gate->reg);
  51. }
  52. out:
  53. spin_unlock_irqrestore(gate->lock, flags);
  54. return ret;
  55. }
  56. static void clk_gate2_disable(struct clk_hw *hw)
  57. {
  58. struct clk_gate2 *gate = to_clk_gate2(hw);
  59. u32 reg;
  60. unsigned long flags;
  61. spin_lock_irqsave(gate->lock, flags);
  62. if (gate->share_count) {
  63. if (WARN_ON(*gate->share_count == 0))
  64. goto out;
  65. else if (--(*gate->share_count) > 0)
  66. goto out;
  67. }
  68. if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
  69. clk_gate_ops.disable(hw);
  70. } else {
  71. reg = readl(gate->reg);
  72. reg &= ~(3 << gate->bit_idx);
  73. writel(reg, gate->reg);
  74. }
  75. out:
  76. spin_unlock_irqrestore(gate->lock, flags);
  77. }
  78. static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
  79. {
  80. u32 val = readl(reg);
  81. if (((val >> bit_idx) & 1) == 1)
  82. return 1;
  83. return 0;
  84. }
  85. static int clk_gate2_is_enabled(struct clk_hw *hw)
  86. {
  87. struct clk_gate2 *gate = to_clk_gate2(hw);
  88. if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
  89. return clk_gate_ops.is_enabled(hw);
  90. return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
  91. }
  92. static void clk_gate2_disable_unused(struct clk_hw *hw)
  93. {
  94. struct clk_gate2 *gate = to_clk_gate2(hw);
  95. unsigned long flags;
  96. u32 reg;
  97. if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
  98. return;
  99. spin_lock_irqsave(gate->lock, flags);
  100. if (!gate->share_count || *gate->share_count == 0) {
  101. reg = readl(gate->reg);
  102. reg &= ~(3 << gate->bit_idx);
  103. writel(reg, gate->reg);
  104. }
  105. spin_unlock_irqrestore(gate->lock, flags);
  106. }
  107. static const struct clk_ops clk_gate2_ops = {
  108. .enable = clk_gate2_enable,
  109. .disable = clk_gate2_disable,
  110. .disable_unused = clk_gate2_disable_unused,
  111. .is_enabled = clk_gate2_is_enabled,
  112. };
  113. struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
  114. const char *parent_name, unsigned long flags,
  115. void __iomem *reg, u8 bit_idx, u8 cgr_val,
  116. u8 clk_gate2_flags, spinlock_t *lock,
  117. unsigned int *share_count)
  118. {
  119. struct clk_gate2 *gate;
  120. struct clk_hw *hw;
  121. struct clk_init_data init;
  122. int ret;
  123. gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
  124. if (!gate)
  125. return ERR_PTR(-ENOMEM);
  126. /* struct clk_gate2 assignments */
  127. gate->reg = reg;
  128. gate->bit_idx = bit_idx;
  129. gate->cgr_val = cgr_val;
  130. gate->flags = clk_gate2_flags;
  131. gate->lock = lock;
  132. gate->share_count = share_count;
  133. init.name = name;
  134. init.ops = &clk_gate2_ops;
  135. init.flags = flags;
  136. init.parent_names = parent_name ? &parent_name : NULL;
  137. init.num_parents = parent_name ? 1 : 0;
  138. gate->hw.init = &init;
  139. hw = &gate->hw;
  140. ret = clk_hw_register(dev, hw);
  141. if (ret) {
  142. kfree(gate);
  143. return ERR_PTR(ret);
  144. }
  145. return hw;
  146. }
  147. EXPORT_SYMBOL_GPL(clk_hw_register_gate2);