clk-frac-pll.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2018 NXP.
  4. *
  5. * This driver supports the fractional plls found in the imx8m SOCs
  6. *
  7. * Documentation for this fractional pll can be found at:
  8. * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/err.h>
  12. #include <linux/export.h>
  13. #include <linux/io.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/slab.h>
  16. #include <linux/bitfield.h>
  17. #include "clk.h"
  18. #define PLL_CFG0 0x0
  19. #define PLL_CFG1 0x4
  20. #define PLL_LOCK_STATUS BIT(31)
  21. #define PLL_PD_MASK BIT(19)
  22. #define PLL_BYPASS_MASK BIT(14)
  23. #define PLL_NEWDIV_VAL BIT(12)
  24. #define PLL_NEWDIV_ACK BIT(11)
  25. #define PLL_FRAC_DIV_MASK GENMASK(30, 7)
  26. #define PLL_INT_DIV_MASK GENMASK(6, 0)
  27. #define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)
  28. #define PLL_FRAC_DENOM 0x1000000
  29. #define PLL_FRAC_LOCK_TIMEOUT 10000
  30. #define PLL_FRAC_ACK_TIMEOUT 500000
  31. struct clk_frac_pll {
  32. struct clk_hw hw;
  33. void __iomem *base;
  34. };
  35. #define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
  36. static int clk_wait_lock(struct clk_frac_pll *pll)
  37. {
  38. u32 val;
  39. return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
  40. PLL_FRAC_LOCK_TIMEOUT);
  41. }
  42. static int clk_wait_ack(struct clk_frac_pll *pll)
  43. {
  44. u32 val;
  45. /* return directly if the pll is in powerdown or in bypass */
  46. if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
  47. return 0;
  48. /* Wait for the pll's divfi and divff to be reloaded */
  49. return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
  50. PLL_FRAC_ACK_TIMEOUT);
  51. }
  52. static int clk_pll_prepare(struct clk_hw *hw)
  53. {
  54. struct clk_frac_pll *pll = to_clk_frac_pll(hw);
  55. u32 val;
  56. val = readl_relaxed(pll->base + PLL_CFG0);
  57. val &= ~PLL_PD_MASK;
  58. writel_relaxed(val, pll->base + PLL_CFG0);
  59. return clk_wait_lock(pll);
  60. }
  61. static void clk_pll_unprepare(struct clk_hw *hw)
  62. {
  63. struct clk_frac_pll *pll = to_clk_frac_pll(hw);
  64. u32 val;
  65. val = readl_relaxed(pll->base + PLL_CFG0);
  66. val |= PLL_PD_MASK;
  67. writel_relaxed(val, pll->base + PLL_CFG0);
  68. }
  69. static int clk_pll_is_prepared(struct clk_hw *hw)
  70. {
  71. struct clk_frac_pll *pll = to_clk_frac_pll(hw);
  72. u32 val;
  73. val = readl_relaxed(pll->base + PLL_CFG0);
  74. return (val & PLL_PD_MASK) ? 0 : 1;
  75. }
  76. static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  77. unsigned long parent_rate)
  78. {
  79. struct clk_frac_pll *pll = to_clk_frac_pll(hw);
  80. u32 val, divff, divfi, divq;
  81. u64 temp64 = parent_rate;
  82. u64 rate;
  83. val = readl_relaxed(pll->base + PLL_CFG0);
  84. divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
  85. val = readl_relaxed(pll->base + PLL_CFG1);
  86. divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
  87. divfi = FIELD_GET(PLL_INT_DIV_MASK, val);
  88. temp64 *= 8;
  89. temp64 *= divff;
  90. do_div(temp64, PLL_FRAC_DENOM);
  91. do_div(temp64, divq);
  92. rate = parent_rate * 8 * (divfi + 1);
  93. do_div(rate, divq);
  94. rate += temp64;
  95. return rate;
  96. }
  97. static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  98. unsigned long *prate)
  99. {
  100. u64 parent_rate = *prate;
  101. u32 divff, divfi;
  102. u64 temp64;
  103. parent_rate *= 8;
  104. rate *= 2;
  105. temp64 = rate;
  106. do_div(temp64, parent_rate);
  107. divfi = temp64;
  108. temp64 = rate - divfi * parent_rate;
  109. temp64 *= PLL_FRAC_DENOM;
  110. do_div(temp64, parent_rate);
  111. divff = temp64;
  112. temp64 = parent_rate;
  113. temp64 *= divff;
  114. do_div(temp64, PLL_FRAC_DENOM);
  115. rate = parent_rate * divfi + temp64;
  116. return rate / 2;
  117. }
  118. /*
  119. * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
  120. * (means the PLL output will be divided by 2). So the PLL output can use
  121. * the below formula:
  122. * pllout = parent_rate * 8 / 2 * DIVF_VAL;
  123. * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
  124. */
  125. static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  126. unsigned long parent_rate)
  127. {
  128. struct clk_frac_pll *pll = to_clk_frac_pll(hw);
  129. u32 val, divfi, divff;
  130. u64 temp64;
  131. int ret;
  132. parent_rate *= 8;
  133. rate *= 2;
  134. divfi = rate / parent_rate;
  135. temp64 = parent_rate * divfi;
  136. temp64 = rate - temp64;
  137. temp64 *= PLL_FRAC_DENOM;
  138. do_div(temp64, parent_rate);
  139. divff = temp64;
  140. val = readl_relaxed(pll->base + PLL_CFG1);
  141. val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
  142. val |= (divff << 7) | (divfi - 1);
  143. writel_relaxed(val, pll->base + PLL_CFG1);
  144. val = readl_relaxed(pll->base + PLL_CFG0);
  145. val &= ~0x1f;
  146. writel_relaxed(val, pll->base + PLL_CFG0);
  147. /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
  148. val = readl_relaxed(pll->base + PLL_CFG0);
  149. val |= PLL_NEWDIV_VAL;
  150. writel_relaxed(val, pll->base + PLL_CFG0);
  151. ret = clk_wait_ack(pll);
  152. /* clear the NEV_DIV_VAL */
  153. val = readl_relaxed(pll->base + PLL_CFG0);
  154. val &= ~PLL_NEWDIV_VAL;
  155. writel_relaxed(val, pll->base + PLL_CFG0);
  156. return ret;
  157. }
  158. static const struct clk_ops clk_frac_pll_ops = {
  159. .prepare = clk_pll_prepare,
  160. .unprepare = clk_pll_unprepare,
  161. .is_prepared = clk_pll_is_prepared,
  162. .recalc_rate = clk_pll_recalc_rate,
  163. .round_rate = clk_pll_round_rate,
  164. .set_rate = clk_pll_set_rate,
  165. };
  166. struct clk_hw *imx_clk_hw_frac_pll(const char *name,
  167. const char *parent_name,
  168. void __iomem *base)
  169. {
  170. struct clk_init_data init;
  171. struct clk_frac_pll *pll;
  172. struct clk_hw *hw;
  173. int ret;
  174. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  175. if (!pll)
  176. return ERR_PTR(-ENOMEM);
  177. init.name = name;
  178. init.ops = &clk_frac_pll_ops;
  179. init.flags = 0;
  180. init.parent_names = &parent_name;
  181. init.num_parents = 1;
  182. pll->base = base;
  183. pll->hw.init = &init;
  184. hw = &pll->hw;
  185. ret = clk_hw_register(NULL, hw);
  186. if (ret) {
  187. kfree(pll);
  188. return ERR_PTR(ret);
  189. }
  190. return hw;
  191. }
  192. EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll);