clk-divider-gate.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP.
  4. * Dong Aisheng <aisheng.dong@nxp.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/slab.h>
  10. #include "clk.h"
  11. struct clk_divider_gate {
  12. struct clk_divider divider;
  13. u32 cached_val;
  14. };
  15. static inline struct clk_divider_gate *to_clk_divider_gate(struct clk_hw *hw)
  16. {
  17. struct clk_divider *div = to_clk_divider(hw);
  18. return container_of(div, struct clk_divider_gate, divider);
  19. }
  20. static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw,
  21. unsigned long parent_rate)
  22. {
  23. struct clk_divider *div = to_clk_divider(hw);
  24. unsigned int val;
  25. val = readl(div->reg) >> div->shift;
  26. val &= clk_div_mask(div->width);
  27. if (!val)
  28. return 0;
  29. return divider_recalc_rate(hw, parent_rate, val, div->table,
  30. div->flags, div->width);
  31. }
  32. static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
  33. unsigned long parent_rate)
  34. {
  35. struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
  36. struct clk_divider *div = to_clk_divider(hw);
  37. unsigned long flags;
  38. unsigned int val;
  39. spin_lock_irqsave(div->lock, flags);
  40. if (!clk_hw_is_enabled(hw)) {
  41. val = div_gate->cached_val;
  42. } else {
  43. val = readl(div->reg) >> div->shift;
  44. val &= clk_div_mask(div->width);
  45. }
  46. spin_unlock_irqrestore(div->lock, flags);
  47. if (!val)
  48. return 0;
  49. return divider_recalc_rate(hw, parent_rate, val, div->table,
  50. div->flags, div->width);
  51. }
  52. static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
  53. unsigned long *prate)
  54. {
  55. return clk_divider_ops.round_rate(hw, rate, prate);
  56. }
  57. static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
  58. unsigned long parent_rate)
  59. {
  60. struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
  61. struct clk_divider *div = to_clk_divider(hw);
  62. unsigned long flags;
  63. int value;
  64. u32 val;
  65. value = divider_get_val(rate, parent_rate, div->table,
  66. div->width, div->flags);
  67. if (value < 0)
  68. return value;
  69. spin_lock_irqsave(div->lock, flags);
  70. if (clk_hw_is_enabled(hw)) {
  71. val = readl(div->reg);
  72. val &= ~(clk_div_mask(div->width) << div->shift);
  73. val |= (u32)value << div->shift;
  74. writel(val, div->reg);
  75. } else {
  76. div_gate->cached_val = value;
  77. }
  78. spin_unlock_irqrestore(div->lock, flags);
  79. return 0;
  80. }
  81. static int clk_divider_enable(struct clk_hw *hw)
  82. {
  83. struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
  84. struct clk_divider *div = to_clk_divider(hw);
  85. unsigned long flags;
  86. u32 val;
  87. if (!div_gate->cached_val) {
  88. pr_err("%s: no valid preset rate\n", clk_hw_get_name(hw));
  89. return -EINVAL;
  90. }
  91. spin_lock_irqsave(div->lock, flags);
  92. /* restore div val */
  93. val = readl(div->reg);
  94. val |= div_gate->cached_val << div->shift;
  95. writel(val, div->reg);
  96. spin_unlock_irqrestore(div->lock, flags);
  97. return 0;
  98. }
  99. static void clk_divider_disable(struct clk_hw *hw)
  100. {
  101. struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
  102. struct clk_divider *div = to_clk_divider(hw);
  103. unsigned long flags;
  104. u32 val;
  105. spin_lock_irqsave(div->lock, flags);
  106. /* store the current div val */
  107. val = readl(div->reg) >> div->shift;
  108. val &= clk_div_mask(div->width);
  109. div_gate->cached_val = val;
  110. writel(0, div->reg);
  111. spin_unlock_irqrestore(div->lock, flags);
  112. }
  113. static int clk_divider_is_enabled(struct clk_hw *hw)
  114. {
  115. struct clk_divider *div = to_clk_divider(hw);
  116. u32 val;
  117. val = readl(div->reg) >> div->shift;
  118. val &= clk_div_mask(div->width);
  119. return val ? 1 : 0;
  120. }
  121. static const struct clk_ops clk_divider_gate_ro_ops = {
  122. .recalc_rate = clk_divider_gate_recalc_rate_ro,
  123. .round_rate = clk_divider_round_rate,
  124. };
  125. static const struct clk_ops clk_divider_gate_ops = {
  126. .recalc_rate = clk_divider_gate_recalc_rate,
  127. .round_rate = clk_divider_round_rate,
  128. .set_rate = clk_divider_gate_set_rate,
  129. .enable = clk_divider_enable,
  130. .disable = clk_divider_disable,
  131. .is_enabled = clk_divider_is_enabled,
  132. };
  133. /*
  134. * NOTE: In order to reuse the most code from the common divider,
  135. * we also design our divider following the way that provids an extra
  136. * clk_divider_flags, however it's fixed to CLK_DIVIDER_ONE_BASED by
  137. * default as our HW is. Besides that it supports only CLK_DIVIDER_READ_ONLY
  138. * flag which can be specified by user flexibly.
  139. */
  140. struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
  141. unsigned long flags, void __iomem *reg,
  142. u8 shift, u8 width, u8 clk_divider_flags,
  143. const struct clk_div_table *table,
  144. spinlock_t *lock)
  145. {
  146. struct clk_init_data init;
  147. struct clk_divider_gate *div_gate;
  148. struct clk_hw *hw;
  149. u32 val;
  150. int ret;
  151. div_gate = kzalloc(sizeof(*div_gate), GFP_KERNEL);
  152. if (!div_gate)
  153. return ERR_PTR(-ENOMEM);
  154. init.name = name;
  155. if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
  156. init.ops = &clk_divider_gate_ro_ops;
  157. else
  158. init.ops = &clk_divider_gate_ops;
  159. init.flags = flags;
  160. init.parent_names = parent_name ? &parent_name : NULL;
  161. init.num_parents = parent_name ? 1 : 0;
  162. div_gate->divider.reg = reg;
  163. div_gate->divider.shift = shift;
  164. div_gate->divider.width = width;
  165. div_gate->divider.lock = lock;
  166. div_gate->divider.table = table;
  167. div_gate->divider.hw.init = &init;
  168. div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
  169. /* cache gate status */
  170. val = readl(reg) >> shift;
  171. val &= clk_div_mask(width);
  172. div_gate->cached_val = val;
  173. hw = &div_gate->divider.hw;
  174. ret = clk_hw_register(NULL, hw);
  175. if (ret) {
  176. kfree(div_gate);
  177. hw = ERR_PTR(ret);
  178. }
  179. return hw;
  180. }