clk-composite-8m.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/errno.h>
  7. #include <linux/export.h>
  8. #include <linux/io.h>
  9. #include <linux/slab.h>
  10. #include "clk.h"
  11. #define PCG_PREDIV_SHIFT 16
  12. #define PCG_PREDIV_WIDTH 3
  13. #define PCG_PREDIV_MAX 8
  14. #define PCG_DIV_SHIFT 0
  15. #define PCG_CORE_DIV_WIDTH 3
  16. #define PCG_DIV_WIDTH 6
  17. #define PCG_DIV_MAX 64
  18. #define PCG_PCS_SHIFT 24
  19. #define PCG_PCS_MASK 0x7
  20. #define PCG_CGC_SHIFT 28
  21. static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
  22. unsigned long parent_rate)
  23. {
  24. struct clk_divider *divider = to_clk_divider(hw);
  25. unsigned long prediv_rate;
  26. unsigned int prediv_value;
  27. unsigned int div_value;
  28. prediv_value = readl(divider->reg) >> divider->shift;
  29. prediv_value &= clk_div_mask(divider->width);
  30. prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
  31. NULL, divider->flags,
  32. divider->width);
  33. div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
  34. div_value &= clk_div_mask(PCG_DIV_WIDTH);
  35. return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
  36. divider->flags, PCG_DIV_WIDTH);
  37. }
  38. static int imx8m_clk_composite_compute_dividers(unsigned long rate,
  39. unsigned long parent_rate,
  40. int *prediv, int *postdiv)
  41. {
  42. int div1, div2;
  43. int error = INT_MAX;
  44. int ret = -EINVAL;
  45. *prediv = 1;
  46. *postdiv = 1;
  47. for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
  48. for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
  49. int new_error = ((parent_rate / div1) / div2) - rate;
  50. if (abs(new_error) < abs(error)) {
  51. *prediv = div1;
  52. *postdiv = div2;
  53. error = new_error;
  54. ret = 0;
  55. }
  56. }
  57. }
  58. return ret;
  59. }
  60. static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw,
  61. unsigned long rate,
  62. unsigned long *prate)
  63. {
  64. int prediv_value;
  65. int div_value;
  66. imx8m_clk_composite_compute_dividers(rate, *prate,
  67. &prediv_value, &div_value);
  68. rate = DIV_ROUND_UP(*prate, prediv_value);
  69. return DIV_ROUND_UP(rate, div_value);
  70. }
  71. static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
  72. unsigned long rate,
  73. unsigned long parent_rate)
  74. {
  75. struct clk_divider *divider = to_clk_divider(hw);
  76. unsigned long flags;
  77. int prediv_value;
  78. int div_value;
  79. int ret;
  80. u32 val;
  81. ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
  82. &prediv_value, &div_value);
  83. if (ret)
  84. return -EINVAL;
  85. spin_lock_irqsave(divider->lock, flags);
  86. val = readl(divider->reg);
  87. val &= ~((clk_div_mask(divider->width) << divider->shift) |
  88. (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
  89. val |= (u32)(prediv_value - 1) << divider->shift;
  90. val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
  91. writel(val, divider->reg);
  92. spin_unlock_irqrestore(divider->lock, flags);
  93. return ret;
  94. }
  95. static const struct clk_ops imx8m_clk_composite_divider_ops = {
  96. .recalc_rate = imx8m_clk_composite_divider_recalc_rate,
  97. .round_rate = imx8m_clk_composite_divider_round_rate,
  98. .set_rate = imx8m_clk_composite_divider_set_rate,
  99. };
  100. static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
  101. {
  102. return clk_mux_ops.get_parent(hw);
  103. }
  104. static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
  105. {
  106. struct clk_mux *mux = to_clk_mux(hw);
  107. u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
  108. unsigned long flags = 0;
  109. u32 reg;
  110. if (mux->lock)
  111. spin_lock_irqsave(mux->lock, flags);
  112. reg = readl(mux->reg);
  113. reg &= ~(mux->mask << mux->shift);
  114. val = val << mux->shift;
  115. reg |= val;
  116. /*
  117. * write twice to make sure non-target interface
  118. * SEL_A/B point the same clk input.
  119. */
  120. writel(reg, mux->reg);
  121. writel(reg, mux->reg);
  122. if (mux->lock)
  123. spin_unlock_irqrestore(mux->lock, flags);
  124. return 0;
  125. }
  126. static int
  127. imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
  128. struct clk_rate_request *req)
  129. {
  130. return clk_mux_ops.determine_rate(hw, req);
  131. }
  132. static const struct clk_ops imx8m_clk_composite_mux_ops = {
  133. .get_parent = imx8m_clk_composite_mux_get_parent,
  134. .set_parent = imx8m_clk_composite_mux_set_parent,
  135. .determine_rate = imx8m_clk_composite_mux_determine_rate,
  136. };
  137. struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
  138. const char * const *parent_names,
  139. int num_parents, void __iomem *reg,
  140. u32 composite_flags,
  141. unsigned long flags)
  142. {
  143. struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
  144. struct clk_hw *div_hw, *gate_hw;
  145. struct clk_divider *div = NULL;
  146. struct clk_gate *gate = NULL;
  147. struct clk_mux *mux = NULL;
  148. const struct clk_ops *divider_ops;
  149. const struct clk_ops *mux_ops;
  150. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  151. if (!mux)
  152. goto fail;
  153. mux_hw = &mux->hw;
  154. mux->reg = reg;
  155. mux->shift = PCG_PCS_SHIFT;
  156. mux->mask = PCG_PCS_MASK;
  157. mux->lock = &imx_ccm_lock;
  158. div = kzalloc(sizeof(*div), GFP_KERNEL);
  159. if (!div)
  160. goto fail;
  161. div_hw = &div->hw;
  162. div->reg = reg;
  163. if (composite_flags & IMX_COMPOSITE_CORE) {
  164. div->shift = PCG_DIV_SHIFT;
  165. div->width = PCG_CORE_DIV_WIDTH;
  166. divider_ops = &clk_divider_ops;
  167. mux_ops = &imx8m_clk_composite_mux_ops;
  168. } else if (composite_flags & IMX_COMPOSITE_BUS) {
  169. div->shift = PCG_PREDIV_SHIFT;
  170. div->width = PCG_PREDIV_WIDTH;
  171. divider_ops = &imx8m_clk_composite_divider_ops;
  172. mux_ops = &imx8m_clk_composite_mux_ops;
  173. } else {
  174. div->shift = PCG_PREDIV_SHIFT;
  175. div->width = PCG_PREDIV_WIDTH;
  176. divider_ops = &imx8m_clk_composite_divider_ops;
  177. mux_ops = &clk_mux_ops;
  178. if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
  179. flags |= CLK_SET_PARENT_GATE;
  180. }
  181. div->lock = &imx_ccm_lock;
  182. div->flags = CLK_DIVIDER_ROUND_CLOSEST;
  183. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  184. if (!gate)
  185. goto fail;
  186. gate_hw = &gate->hw;
  187. gate->reg = reg;
  188. gate->bit_idx = PCG_CGC_SHIFT;
  189. gate->lock = &imx_ccm_lock;
  190. hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
  191. mux_hw, mux_ops, div_hw,
  192. divider_ops, gate_hw, &clk_gate_ops, flags);
  193. if (IS_ERR(hw))
  194. goto fail;
  195. return hw;
  196. fail:
  197. kfree(gate);
  198. kfree(div);
  199. kfree(mux);
  200. return ERR_CAST(hw);
  201. }
  202. EXPORT_SYMBOL_GPL(imx8m_clk_hw_composite_flags);