clk-composite-7ulp.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017~2018 NXP
  5. *
  6. */
  7. #include <linux/bits.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/err.h>
  10. #include <linux/slab.h>
  11. #include "clk.h"
  12. #define PCG_PCS_SHIFT 24
  13. #define PCG_PCS_MASK 0x7
  14. #define PCG_CGC_SHIFT 30
  15. #define PCG_FRAC_SHIFT 3
  16. #define PCG_FRAC_WIDTH 1
  17. #define PCG_FRAC_MASK BIT(3)
  18. #define PCG_PCD_SHIFT 0
  19. #define PCG_PCD_WIDTH 3
  20. #define PCG_PCD_MASK 0x7
  21. struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
  22. const char * const *parent_names,
  23. int num_parents, bool mux_present,
  24. bool rate_present, bool gate_present,
  25. void __iomem *reg)
  26. {
  27. struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
  28. struct clk_fractional_divider *fd = NULL;
  29. struct clk_gate *gate = NULL;
  30. struct clk_mux *mux = NULL;
  31. struct clk_hw *hw;
  32. if (mux_present) {
  33. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  34. if (!mux)
  35. return ERR_PTR(-ENOMEM);
  36. mux_hw = &mux->hw;
  37. mux->reg = reg;
  38. mux->shift = PCG_PCS_SHIFT;
  39. mux->mask = PCG_PCS_MASK;
  40. }
  41. if (rate_present) {
  42. fd = kzalloc(sizeof(*fd), GFP_KERNEL);
  43. if (!fd) {
  44. kfree(mux);
  45. return ERR_PTR(-ENOMEM);
  46. }
  47. fd_hw = &fd->hw;
  48. fd->reg = reg;
  49. fd->mshift = PCG_FRAC_SHIFT;
  50. fd->mwidth = PCG_FRAC_WIDTH;
  51. fd->mmask = PCG_FRAC_MASK;
  52. fd->nshift = PCG_PCD_SHIFT;
  53. fd->nwidth = PCG_PCD_WIDTH;
  54. fd->nmask = PCG_PCD_MASK;
  55. fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
  56. }
  57. if (gate_present) {
  58. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  59. if (!gate) {
  60. kfree(mux);
  61. kfree(fd);
  62. return ERR_PTR(-ENOMEM);
  63. }
  64. gate_hw = &gate->hw;
  65. gate->reg = reg;
  66. gate->bit_idx = PCG_CGC_SHIFT;
  67. }
  68. hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
  69. mux_hw, &clk_mux_ops, fd_hw,
  70. &clk_fractional_divider_ops, gate_hw,
  71. &clk_gate_ops, CLK_SET_RATE_GATE |
  72. CLK_SET_PARENT_GATE);
  73. if (IS_ERR(hw)) {
  74. kfree(mux);
  75. kfree(fd);
  76. kfree(gate);
  77. }
  78. return hw;
  79. }