psc.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Clock driver for TI Davinci PSC controllers
  4. *
  5. * Copyright (C) 2017 David Lechner <david@lechnology.com>
  6. *
  7. * Based on: drivers/clk/keystone/gate.c
  8. * Copyright (C) 2013 Texas Instruments.
  9. * Murali Karicheri <m-karicheri2@ti.com>
  10. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  11. *
  12. * And: arch/arm/mach-davinci/psc.c
  13. * Copyright (C) 2006 Texas Instruments.
  14. */
  15. #include <linux/clk-provider.h>
  16. #include <linux/clk.h>
  17. #include <linux/clk/davinci.h>
  18. #include <linux/clkdev.h>
  19. #include <linux/err.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_clock.h>
  25. #include <linux/pm_domain.h>
  26. #include <linux/regmap.h>
  27. #include <linux/reset-controller.h>
  28. #include <linux/slab.h>
  29. #include <linux/types.h>
  30. #include "psc.h"
  31. /* PSC register offsets */
  32. #define EPCPR 0x070
  33. #define PTCMD 0x120
  34. #define PTSTAT 0x128
  35. #define PDSTAT(n) (0x200 + 4 * (n))
  36. #define PDCTL(n) (0x300 + 4 * (n))
  37. #define MDSTAT(n) (0x800 + 4 * (n))
  38. #define MDCTL(n) (0xa00 + 4 * (n))
  39. /* PSC module states */
  40. enum davinci_lpsc_state {
  41. LPSC_STATE_SWRSTDISABLE = 0,
  42. LPSC_STATE_SYNCRST = 1,
  43. LPSC_STATE_DISABLE = 2,
  44. LPSC_STATE_ENABLE = 3,
  45. };
  46. #define MDSTAT_STATE_MASK GENMASK(5, 0)
  47. #define MDSTAT_MCKOUT BIT(12)
  48. #define PDSTAT_STATE_MASK GENMASK(4, 0)
  49. #define MDCTL_FORCE BIT(31)
  50. #define MDCTL_LRESET BIT(8)
  51. #define PDCTL_EPCGOOD BIT(8)
  52. #define PDCTL_NEXT BIT(0)
  53. struct davinci_psc_data {
  54. struct clk_onecell_data clk_data;
  55. struct genpd_onecell_data pm_data;
  56. struct reset_controller_dev rcdev;
  57. };
  58. /**
  59. * struct davinci_lpsc_clk - LPSC clock structure
  60. * @dev: the device that provides this LPSC or NULL
  61. * @hw: clk_hw for the LPSC
  62. * @pm_domain: power domain for the LPSC
  63. * @genpd_clk: clock reference owned by @pm_domain
  64. * @regmap: PSC MMIO region
  65. * @md: Module domain (LPSC module id)
  66. * @pd: Power domain
  67. * @flags: LPSC_* quirk flags
  68. */
  69. struct davinci_lpsc_clk {
  70. struct device *dev;
  71. struct clk_hw hw;
  72. struct generic_pm_domain pm_domain;
  73. struct clk *genpd_clk;
  74. struct regmap *regmap;
  75. u32 md;
  76. u32 pd;
  77. u32 flags;
  78. };
  79. #define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x)
  80. #define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x)
  81. /**
  82. * best_dev_name - get the "best" device name.
  83. * @dev: the device
  84. *
  85. * Returns the device tree compatible name if the device has a DT node,
  86. * otherwise return the device name. This is mainly needed because clkdev
  87. * lookups are limited to 20 chars for dev_id and when using device tree,
  88. * dev_name(dev) is much longer than that.
  89. */
  90. static inline const char *best_dev_name(struct device *dev)
  91. {
  92. const char *compatible;
  93. if (!of_property_read_string(dev->of_node, "compatible", &compatible))
  94. return compatible;
  95. return dev_name(dev);
  96. }
  97. static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc,
  98. enum davinci_lpsc_state next_state)
  99. {
  100. u32 epcpr, pdstat, mdstat, ptstat;
  101. regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,
  102. next_state);
  103. if (lpsc->flags & LPSC_FORCE)
  104. regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,
  105. MDCTL_FORCE);
  106. regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat);
  107. if ((pdstat & PDSTAT_STATE_MASK) == 0) {
  108. regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT,
  109. PDCTL_NEXT);
  110. regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
  111. regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr,
  112. epcpr & BIT(lpsc->pd), 0, 0);
  113. regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD,
  114. PDCTL_EPCGOOD);
  115. } else {
  116. regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
  117. }
  118. regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat,
  119. !(ptstat & BIT(lpsc->pd)), 0, 0);
  120. regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,
  121. (mdstat & MDSTAT_STATE_MASK) == next_state,
  122. 0, 0);
  123. }
  124. static int davinci_lpsc_clk_enable(struct clk_hw *hw)
  125. {
  126. struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
  127. davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE);
  128. return 0;
  129. }
  130. static void davinci_lpsc_clk_disable(struct clk_hw *hw)
  131. {
  132. struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
  133. davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE);
  134. }
  135. static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw)
  136. {
  137. struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
  138. u32 mdstat;
  139. regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);
  140. return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
  141. }
  142. static const struct clk_ops davinci_lpsc_clk_ops = {
  143. .enable = davinci_lpsc_clk_enable,
  144. .disable = davinci_lpsc_clk_disable,
  145. .is_enabled = davinci_lpsc_clk_is_enabled,
  146. };
  147. static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain,
  148. struct device *dev)
  149. {
  150. struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
  151. struct clk *clk;
  152. int ret;
  153. /*
  154. * pm_clk_remove_clk() will call clk_put(), so we have to use clk_get()
  155. * to get the clock instead of using lpsc->hw.clk directly.
  156. */
  157. clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw));
  158. if (IS_ERR(clk))
  159. return (PTR_ERR(clk));
  160. ret = pm_clk_create(dev);
  161. if (ret < 0)
  162. goto fail_clk_put;
  163. ret = pm_clk_add_clk(dev, clk);
  164. if (ret < 0)
  165. goto fail_pm_clk_destroy;
  166. lpsc->genpd_clk = clk;
  167. return 0;
  168. fail_pm_clk_destroy:
  169. pm_clk_destroy(dev);
  170. fail_clk_put:
  171. clk_put(clk);
  172. return ret;
  173. }
  174. static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
  175. struct device *dev)
  176. {
  177. struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
  178. pm_clk_remove_clk(dev, lpsc->genpd_clk);
  179. pm_clk_destroy(dev);
  180. lpsc->genpd_clk = NULL;
  181. }
  182. /**
  183. * davinci_lpsc_clk_register - register LPSC clock
  184. * @dev: the clocks's device or NULL
  185. * @name: name of this clock
  186. * @parent_name: name of clock's parent
  187. * @regmap: PSC MMIO region
  188. * @md: local PSC number
  189. * @pd: power domain
  190. * @flags: LPSC_* flags
  191. */
  192. static struct davinci_lpsc_clk *
  193. davinci_lpsc_clk_register(struct device *dev, const char *name,
  194. const char *parent_name, struct regmap *regmap,
  195. u32 md, u32 pd, u32 flags)
  196. {
  197. struct clk_init_data init;
  198. struct davinci_lpsc_clk *lpsc;
  199. int ret;
  200. bool is_on;
  201. lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL);
  202. if (!lpsc)
  203. return ERR_PTR(-ENOMEM);
  204. init.name = name;
  205. init.ops = &davinci_lpsc_clk_ops;
  206. init.parent_names = (parent_name ? &parent_name : NULL);
  207. init.num_parents = (parent_name ? 1 : 0);
  208. init.flags = 0;
  209. if (flags & LPSC_ALWAYS_ENABLED)
  210. init.flags |= CLK_IS_CRITICAL;
  211. if (flags & LPSC_SET_RATE_PARENT)
  212. init.flags |= CLK_SET_RATE_PARENT;
  213. lpsc->dev = dev;
  214. lpsc->regmap = regmap;
  215. lpsc->hw.init = &init;
  216. lpsc->md = md;
  217. lpsc->pd = pd;
  218. lpsc->flags = flags;
  219. ret = clk_hw_register(dev, &lpsc->hw);
  220. if (ret < 0) {
  221. kfree(lpsc);
  222. return ERR_PTR(ret);
  223. }
  224. /* for now, genpd is only registered when using device-tree */
  225. if (!dev || !dev->of_node)
  226. return lpsc;
  227. /* genpd attach needs a way to look up this clock */
  228. ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
  229. lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s",
  230. best_dev_name(dev), name);
  231. lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev;
  232. lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev;
  233. lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK;
  234. is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw);
  235. pm_genpd_init(&lpsc->pm_domain, NULL, is_on);
  236. return lpsc;
  237. }
  238. static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
  239. {
  240. struct clk_hw *hw = __clk_get_hw(clk);
  241. struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
  242. u32 mdctl;
  243. if (IS_ERR_OR_NULL(lpsc))
  244. return -EINVAL;
  245. mdctl = reset ? 0 : MDCTL_LRESET;
  246. regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);
  247. return 0;
  248. }
  249. static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
  250. unsigned long id)
  251. {
  252. struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
  253. struct clk *clk = psc->clk_data.clks[id];
  254. return davinci_lpsc_clk_reset(clk, true);
  255. }
  256. static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev,
  257. unsigned long id)
  258. {
  259. struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
  260. struct clk *clk = psc->clk_data.clks[id];
  261. return davinci_lpsc_clk_reset(clk, false);
  262. }
  263. static const struct reset_control_ops davinci_psc_reset_ops = {
  264. .assert = davinci_psc_reset_assert,
  265. .deassert = davinci_psc_reset_deassert,
  266. };
  267. static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev,
  268. const struct of_phandle_args *reset_spec)
  269. {
  270. struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */
  271. struct clk *clk;
  272. struct clk_hw *hw;
  273. struct davinci_lpsc_clk *lpsc;
  274. /* the clock node is the same as the reset node */
  275. clk = of_clk_get_from_provider(&clkspec);
  276. if (IS_ERR(clk))
  277. return PTR_ERR(clk);
  278. hw = __clk_get_hw(clk);
  279. lpsc = to_davinci_lpsc_clk(hw);
  280. clk_put(clk);
  281. /* not all modules support local reset */
  282. if (!(lpsc->flags & LPSC_LOCAL_RESET))
  283. return -EINVAL;
  284. return lpsc->md;
  285. }
  286. static const struct regmap_config davinci_psc_regmap_config = {
  287. .reg_bits = 32,
  288. .reg_stride = 4,
  289. .val_bits = 32,
  290. };
  291. static struct davinci_psc_data *
  292. __davinci_psc_register_clocks(struct device *dev,
  293. const struct davinci_lpsc_clk_info *info,
  294. int num_clks,
  295. void __iomem *base)
  296. {
  297. struct davinci_psc_data *psc;
  298. struct clk **clks;
  299. struct generic_pm_domain **pm_domains;
  300. struct regmap *regmap;
  301. int i, ret;
  302. psc = kzalloc(sizeof(*psc), GFP_KERNEL);
  303. if (!psc)
  304. return ERR_PTR(-ENOMEM);
  305. clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL);
  306. if (!clks) {
  307. ret = -ENOMEM;
  308. goto err_free_psc;
  309. }
  310. psc->clk_data.clks = clks;
  311. psc->clk_data.clk_num = num_clks;
  312. /*
  313. * init array with error so that of_clk_src_onecell_get() doesn't
  314. * return NULL for gaps in the sparse array
  315. */
  316. for (i = 0; i < num_clks; i++)
  317. clks[i] = ERR_PTR(-ENOENT);
  318. pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL);
  319. if (!pm_domains) {
  320. ret = -ENOMEM;
  321. goto err_free_clks;
  322. }
  323. psc->pm_data.domains = pm_domains;
  324. psc->pm_data.num_domains = num_clks;
  325. regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
  326. if (IS_ERR(regmap)) {
  327. ret = PTR_ERR(regmap);
  328. goto err_free_pm_domains;
  329. }
  330. for (; info->name; info++) {
  331. struct davinci_lpsc_clk *lpsc;
  332. lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent,
  333. regmap, info->md, info->pd,
  334. info->flags);
  335. if (IS_ERR(lpsc)) {
  336. dev_warn(dev, "Failed to register %s (%ld)\n",
  337. info->name, PTR_ERR(lpsc));
  338. continue;
  339. }
  340. clks[info->md] = lpsc->hw.clk;
  341. pm_domains[info->md] = &lpsc->pm_domain;
  342. }
  343. /*
  344. * for now, a reset controller is only registered when there is a device
  345. * to associate it with.
  346. */
  347. if (!dev)
  348. return psc;
  349. psc->rcdev.ops = &davinci_psc_reset_ops;
  350. psc->rcdev.owner = THIS_MODULE;
  351. psc->rcdev.dev = dev;
  352. psc->rcdev.of_node = dev->of_node;
  353. psc->rcdev.of_reset_n_cells = 1;
  354. psc->rcdev.of_xlate = davinci_psc_reset_of_xlate;
  355. psc->rcdev.nr_resets = num_clks;
  356. ret = devm_reset_controller_register(dev, &psc->rcdev);
  357. if (ret < 0)
  358. dev_warn(dev, "Failed to register reset controller (%d)\n", ret);
  359. return psc;
  360. err_free_pm_domains:
  361. kfree(pm_domains);
  362. err_free_clks:
  363. kfree(clks);
  364. err_free_psc:
  365. kfree(psc);
  366. return ERR_PTR(ret);
  367. }
  368. int davinci_psc_register_clocks(struct device *dev,
  369. const struct davinci_lpsc_clk_info *info,
  370. u8 num_clks,
  371. void __iomem *base)
  372. {
  373. struct davinci_psc_data *psc;
  374. psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
  375. if (IS_ERR(psc))
  376. return PTR_ERR(psc);
  377. for (; info->name; info++) {
  378. const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs;
  379. struct clk *clk = psc->clk_data.clks[info->md];
  380. if (!cdevs || IS_ERR_OR_NULL(clk))
  381. continue;
  382. for (; cdevs->con_id || cdevs->dev_id; cdevs++)
  383. clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id);
  384. }
  385. return 0;
  386. }
  387. int of_davinci_psc_clk_init(struct device *dev,
  388. const struct davinci_lpsc_clk_info *info,
  389. u8 num_clks,
  390. void __iomem *base)
  391. {
  392. struct device_node *node = dev->of_node;
  393. struct davinci_psc_data *psc;
  394. psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
  395. if (IS_ERR(psc))
  396. return PTR_ERR(psc);
  397. of_genpd_add_provider_onecell(node, &psc->pm_data);
  398. of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data);
  399. return 0;
  400. }
  401. static const struct of_device_id davinci_psc_of_match[] = {
  402. #ifdef CONFIG_ARCH_DAVINCI_DA850
  403. { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
  404. { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
  405. #endif
  406. { }
  407. };
  408. static const struct platform_device_id davinci_psc_id_table[] = {
  409. #ifdef CONFIG_ARCH_DAVINCI_DA830
  410. { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
  411. { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
  412. #endif
  413. #ifdef CONFIG_ARCH_DAVINCI_DA850
  414. { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
  415. { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
  416. #endif
  417. #ifdef CONFIG_ARCH_DAVINCI_DM355
  418. { .name = "dm355-psc", .driver_data = (kernel_ulong_t)&dm355_psc_init_data },
  419. #endif
  420. #ifdef CONFIG_ARCH_DAVINCI_DM365
  421. { .name = "dm365-psc", .driver_data = (kernel_ulong_t)&dm365_psc_init_data },
  422. #endif
  423. #ifdef CONFIG_ARCH_DAVINCI_DM644x
  424. { .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
  425. #endif
  426. #ifdef CONFIG_ARCH_DAVINCI_DM646x
  427. { .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
  428. #endif
  429. { }
  430. };
  431. static int davinci_psc_probe(struct platform_device *pdev)
  432. {
  433. struct device *dev = &pdev->dev;
  434. const struct of_device_id *of_id;
  435. const struct davinci_psc_init_data *init_data = NULL;
  436. void __iomem *base;
  437. int ret;
  438. of_id = of_match_device(davinci_psc_of_match, dev);
  439. if (of_id)
  440. init_data = of_id->data;
  441. else if (pdev->id_entry)
  442. init_data = (void *)pdev->id_entry->driver_data;
  443. if (!init_data) {
  444. dev_err(dev, "unable to find driver init data\n");
  445. return -EINVAL;
  446. }
  447. base = devm_platform_ioremap_resource(pdev, 0);
  448. if (IS_ERR(base))
  449. return PTR_ERR(base);
  450. ret = devm_clk_bulk_get(dev, init_data->num_parent_clks,
  451. init_data->parent_clks);
  452. if (ret < 0)
  453. return ret;
  454. return init_data->psc_init(dev, base);
  455. }
  456. static struct platform_driver davinci_psc_driver = {
  457. .probe = davinci_psc_probe,
  458. .driver = {
  459. .name = "davinci-psc-clk",
  460. .of_match_table = davinci_psc_of_match,
  461. },
  462. .id_table = davinci_psc_id_table,
  463. };
  464. static int __init davinci_psc_driver_init(void)
  465. {
  466. return platform_driver_register(&davinci_psc_driver);
  467. }
  468. /* has to be postcore_initcall because davinci_gpio depend on PSC clocks */
  469. postcore_initcall(davinci_psc_driver_init);