psc-dm365.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PSC clock descriptions for TI DaVinci DM365
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/davinci.h>
  9. #include <linux/clk.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/init.h>
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include "psc.h"
  15. LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
  16. LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
  17. LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
  18. LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
  19. LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
  20. LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
  21. LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL,
  22. NULL, "ti-aemif");
  23. LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
  24. LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
  25. LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
  26. LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
  27. LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
  28. /* REVISIT: gpio-davinci.c should be modified to drop con_id */
  29. LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
  30. LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
  31. LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
  32. LPSC_CLKDEV1(spi3_clkdev, NULL, "spi_davinci.3");
  33. LPSC_CLKDEV1(spi4_clkdev, NULL, "spi_davinci.4");
  34. LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
  35. "fck", "davinci_mdio.0");
  36. LPSC_CLKDEV1(voice_codec_clkdev, NULL, "davinci_voicecodec");
  37. LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
  38. LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
  39. static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
  40. LPSC(1, 0, vpss_slave, pll1_sysclk5, vpss_slave_clkdev, 0),
  41. LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
  42. LPSC(6, 0, spi1, pll1_sysclk4, spi1_clkdev, 0),
  43. LPSC(7, 0, mmcsd1, pll1_sysclk4, mmcsd1_clkdev, 0),
  44. LPSC(8, 0, asp0, pll1_sysclk4, asp0_clkdev, 0),
  45. LPSC(9, 0, usb, pll1_auxclk, usb_clkdev, 0),
  46. LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
  47. LPSC(11, 0, spi2, pll1_sysclk4, spi2_clkdev, 0),
  48. LPSC(12, 0, rto, pll1_sysclk4, NULL, 0),
  49. LPSC(14, 0, aemif, pll1_sysclk4, aemif_clkdev, 0),
  50. LPSC(15, 0, mmcsd0, pll1_sysclk8, mmcsd0_clkdev, 0),
  51. LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
  52. LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
  53. LPSC(20, 0, uart1, pll1_sysclk4, uart1_clkdev, 0),
  54. LPSC(22, 0, spi0, pll1_sysclk4, spi0_clkdev, 0),
  55. LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
  56. LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
  57. LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
  58. LPSC(26, 0, gpio, pll1_sysclk4, gpio_clkdev, 0),
  59. LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
  60. LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
  61. /* REVISIT: why can't this be disabled? */
  62. LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
  63. LPSC(31, 0, arm, pll2_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  64. LPSC(38, 0, spi3, pll1_sysclk4, spi3_clkdev, 0),
  65. LPSC(39, 0, spi4, pll1_auxclk, spi4_clkdev, 0),
  66. LPSC(40, 0, emac, pll1_sysclk4, emac_clkdev, 0),
  67. /*
  68. * The TRM (ARM Subsystem User's Guide) shows two clocks input into
  69. * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
  70. * not fully clear from documentation which clock should be considered
  71. * as parent for PSC. The clock chosen here is to maintain
  72. * compatibility with existing code in arch/arm/mach-davinci/dm365.c
  73. */
  74. LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
  75. /*
  76. * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
  77. * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
  78. * into HDVICP and MJCP. The clock chosen here is to remain compatible
  79. * with code existing in arch/arm/mach-davinci/dm365.c
  80. */
  81. LPSC(46, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
  82. LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
  83. LPSC(50, 0, mjcp, pll1_sysclk3, NULL, 0),
  84. { }
  85. };
  86. int dm365_psc_init(struct device *dev, void __iomem *base)
  87. {
  88. return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
  89. }
  90. static struct clk_bulk_data dm365_psc_parent_clks[] = {
  91. { .id = "pll1_sysclk1" },
  92. { .id = "pll1_sysclk3" },
  93. { .id = "pll1_sysclk4" },
  94. { .id = "pll1_sysclk5" },
  95. { .id = "pll1_sysclk8" },
  96. { .id = "pll2_sysclk2" },
  97. { .id = "pll2_sysclk4" },
  98. { .id = "pll1_auxclk" },
  99. };
  100. const struct davinci_psc_init_data dm365_psc_init_data = {
  101. .parent_clks = dm365_psc_parent_clks,
  102. .num_parent_clks = ARRAY_SIZE(dm365_psc_parent_clks),
  103. .psc_init = &dm365_psc_init,
  104. };