psc-da830.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk.h>
  9. #include <linux/clkdev.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include "psc.h"
  14. LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif");
  15. LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
  16. LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0");
  17. LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
  18. static const struct davinci_lpsc_clk_info da830_psc0_info[] = {
  19. LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  20. LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  21. LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  22. LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
  23. LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
  24. LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0),
  25. LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
  26. LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  27. LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
  28. LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
  29. LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  30. LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  31. LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  32. LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
  33. LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED),
  34. { }
  35. };
  36. static int da830_psc0_init(struct device *dev, void __iomem *base)
  37. {
  38. return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base);
  39. }
  40. static struct clk_bulk_data da830_psc0_parent_clks[] = {
  41. { .id = "pll0_sysclk2" },
  42. { .id = "pll0_sysclk3" },
  43. { .id = "pll0_sysclk4" },
  44. { .id = "pll0_sysclk6" },
  45. };
  46. const struct davinci_psc_init_data da830_psc0_init_data = {
  47. .parent_clks = da830_psc0_parent_clks,
  48. .num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks),
  49. .psc_init = &da830_psc0_init,
  50. };
  51. LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
  52. NULL, "musb-da8xx",
  53. NULL, "cppi41-dmaengine");
  54. LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
  55. /* REVISIT: gpio-davinci.c should be modified to drop con_id */
  56. LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
  57. LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
  58. "fck", "davinci_mdio.0");
  59. LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
  60. LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1");
  61. LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2");
  62. LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
  63. LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
  64. LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
  65. LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
  66. LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
  67. LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0",
  68. "fck", "ehrpwm.1");
  69. LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
  70. "fck", "ecap.1",
  71. "fck", "ecap.2");
  72. LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0",
  73. NULL, "eqep.1");
  74. static const struct davinci_lpsc_clk_info da830_psc1_info[] = {
  75. LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
  76. LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
  77. LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
  78. LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
  79. LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED),
  80. LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0),
  81. LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0),
  82. LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0),
  83. LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0),
  84. LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
  85. LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0),
  86. LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0),
  87. LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
  88. LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0),
  89. LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0),
  90. LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0),
  91. { }
  92. };
  93. static int da830_psc1_init(struct device *dev, void __iomem *base)
  94. {
  95. return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base);
  96. }
  97. static struct clk_bulk_data da830_psc1_parent_clks[] = {
  98. { .id = "pll0_sysclk2" },
  99. { .id = "pll0_sysclk4" },
  100. { .id = "pll0_sysclk5" },
  101. };
  102. const struct davinci_psc_init_data da830_psc1_init_data = {
  103. .parent_clks = da830_psc1_parent_clks,
  104. .num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks),
  105. .psc_init = &da830_psc1_init,
  106. };