pll.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Clock driver for TI Davinci PSC controllers
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #ifndef __CLK_DAVINCI_PLL_H___
  8. #define __CLK_DAVINCI_PLL_H___
  9. #include <linux/bitops.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/of.h>
  12. #include <linux/regmap.h>
  13. #include <linux/types.h>
  14. #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
  15. #define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */
  16. #define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */
  17. #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */
  18. #define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */
  19. #define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */
  20. #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */
  21. #define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */
  22. #define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */
  23. #define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */
  24. /** davinci_pll_clk_info - controller-specific PLL info
  25. * @name: The name of the PLL
  26. * @unlock_reg: Option CFGCHIP register for unlocking PLL
  27. * @unlock_mask: Bitmask used with @unlock_reg
  28. * @pllm_mask: Bitmask for PLLM[PLLM] value
  29. * @pllm_min: Minimum allowable value for PLLM[PLLM]
  30. * @pllm_max: Maximum allowable value for PLLM[PLLM]
  31. * @pllout_min_rate: Minimum allowable rate for PLLOUT
  32. * @pllout_max_rate: Maximum allowable rate for PLLOUT
  33. * @flags: Bitmap of PLL_* flags.
  34. */
  35. struct davinci_pll_clk_info {
  36. const char *name;
  37. u32 unlock_reg;
  38. u32 unlock_mask;
  39. u32 pllm_mask;
  40. u32 pllm_min;
  41. u32 pllm_max;
  42. unsigned long pllout_min_rate;
  43. unsigned long pllout_max_rate;
  44. u32 flags;
  45. };
  46. #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */
  47. #define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */
  48. #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */
  49. /** davinci_pll_sysclk_info - SYSCLKn-specific info
  50. * @name: The name of the clock
  51. * @parent_name: The name of the parent clock
  52. * @id: "n" in "SYSCLKn"
  53. * @ratio_width: Width (in bits) of RATIO in PLLDIVn register
  54. * @flags: Bitmap of SYSCLK_* flags.
  55. */
  56. struct davinci_pll_sysclk_info {
  57. const char *name;
  58. const char *parent_name;
  59. u32 id;
  60. u32 ratio_width;
  61. u32 flags;
  62. };
  63. #define SYSCLK(i, n, p, w, f) \
  64. static const struct davinci_pll_sysclk_info n = { \
  65. .name = #n, \
  66. .parent_name = #p, \
  67. .id = (i), \
  68. .ratio_width = (w), \
  69. .flags = (f), \
  70. }
  71. /** davinci_pll_obsclk_info - OBSCLK-specific info
  72. * @name: The name of the clock
  73. * @parent_names: Array of names of the parent clocks
  74. * @num_parents: Length of @parent_names
  75. * @table: Array of values to write to OCSEL[OCSRC] cooresponding to
  76. * @parent_names
  77. * @ocsrc_mask: Bitmask for OCSEL[OCSRC]
  78. */
  79. struct davinci_pll_obsclk_info {
  80. const char *name;
  81. const char * const *parent_names;
  82. u8 num_parents;
  83. u32 *table;
  84. u32 ocsrc_mask;
  85. };
  86. struct clk *davinci_pll_clk_register(struct device *dev,
  87. const struct davinci_pll_clk_info *info,
  88. const char *parent_name,
  89. void __iomem *base,
  90. struct regmap *cfgchip);
  91. struct clk *davinci_pll_auxclk_register(struct device *dev,
  92. const char *name,
  93. void __iomem *base);
  94. struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
  95. const char *name,
  96. void __iomem *base);
  97. struct clk *
  98. davinci_pll_obsclk_register(struct device *dev,
  99. const struct davinci_pll_obsclk_info *info,
  100. void __iomem *base);
  101. struct clk *
  102. davinci_pll_sysclk_register(struct device *dev,
  103. const struct davinci_pll_sysclk_info *info,
  104. void __iomem *base);
  105. int of_davinci_pll_init(struct device *dev, struct device_node *node,
  106. const struct davinci_pll_clk_info *info,
  107. const struct davinci_pll_obsclk_info *obsclk_info,
  108. const struct davinci_pll_sysclk_info **div_info,
  109. u8 max_sysclk_id,
  110. void __iomem *base,
  111. struct regmap *cfgchip);
  112. /* Platform-specific callbacks */
  113. #ifdef CONFIG_ARCH_DAVINCI_DA850
  114. int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
  115. void of_da850_pll0_init(struct device_node *node);
  116. int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
  117. #endif
  118. #ifdef CONFIG_ARCH_DAVINCI_DM355
  119. int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
  120. #endif
  121. #ifdef CONFIG_ARCH_DAVINCI_DM644x
  122. int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
  123. #endif
  124. #ifdef CONFIG_ARCH_DAVINCI_DM646x
  125. int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
  126. #endif
  127. #endif /* __CLK_DAVINCI_PLL_H___ */