pll.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PLL clock driver for TI Davinci SoCs
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. *
  7. * Based on arch/arm/mach-davinci/clock.c
  8. * Copyright (C) 2006-2007 Texas Instruments.
  9. * Copyright (C) 2008-2009 Deep Root Systems, LLC
  10. */
  11. #include <linux/clk-provider.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk/davinci.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/notifier.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of.h>
  23. #include <linux/platform_data/clk-davinci-pll.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/regmap.h>
  26. #include <linux/slab.h>
  27. #include <linux/types.h>
  28. #include "pll.h"
  29. #define MAX_NAME_SIZE 20
  30. #define OSCIN_CLK_NAME "oscin"
  31. #define REVID 0x000
  32. #define PLLCTL 0x100
  33. #define OCSEL 0x104
  34. #define PLLSECCTL 0x108
  35. #define PLLM 0x110
  36. #define PREDIV 0x114
  37. #define PLLDIV1 0x118
  38. #define PLLDIV2 0x11c
  39. #define PLLDIV3 0x120
  40. #define OSCDIV 0x124
  41. #define POSTDIV 0x128
  42. #define BPDIV 0x12c
  43. #define PLLCMD 0x138
  44. #define PLLSTAT 0x13c
  45. #define ALNCTL 0x140
  46. #define DCHANGE 0x144
  47. #define CKEN 0x148
  48. #define CKSTAT 0x14c
  49. #define SYSTAT 0x150
  50. #define PLLDIV4 0x160
  51. #define PLLDIV5 0x164
  52. #define PLLDIV6 0x168
  53. #define PLLDIV7 0x16c
  54. #define PLLDIV8 0x170
  55. #define PLLDIV9 0x174
  56. #define PLLCTL_PLLEN BIT(0)
  57. #define PLLCTL_PLLPWRDN BIT(1)
  58. #define PLLCTL_PLLRST BIT(3)
  59. #define PLLCTL_PLLDIS BIT(4)
  60. #define PLLCTL_PLLENSRC BIT(5)
  61. #define PLLCTL_CLKMODE BIT(8)
  62. /* shared by most *DIV registers */
  63. #define DIV_RATIO_SHIFT 0
  64. #define DIV_RATIO_WIDTH 5
  65. #define DIV_ENABLE_SHIFT 15
  66. #define PLLCMD_GOSET BIT(0)
  67. #define PLLSTAT_GOSTAT BIT(0)
  68. #define CKEN_OBSCLK_SHIFT 1
  69. #define CKEN_AUXEN_SHIFT 0
  70. /*
  71. * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  72. * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
  73. * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
  74. * is ~25MHz. Units are micro seconds.
  75. */
  76. #define PLL_BYPASS_TIME 1
  77. /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
  78. #define PLL_RESET_TIME 1
  79. /*
  80. * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
  81. * Units are micro seconds.
  82. */
  83. #define PLL_LOCK_TIME 20
  84. /**
  85. * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
  86. * @hw: clk_hw for the pll
  87. * @base: Base memory address
  88. * @pllm_min: The minimum allowable PLLM[PLLM] value
  89. * @pllm_max: The maxiumum allowable PLLM[PLLM] value
  90. * @pllm_mask: Bitmask for PLLM[PLLM] value
  91. */
  92. struct davinci_pll_clk {
  93. struct clk_hw hw;
  94. void __iomem *base;
  95. u32 pllm_min;
  96. u32 pllm_max;
  97. u32 pllm_mask;
  98. };
  99. #define to_davinci_pll_clk(_hw) \
  100. container_of((_hw), struct davinci_pll_clk, hw)
  101. static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw,
  102. unsigned long parent_rate)
  103. {
  104. struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
  105. unsigned long rate = parent_rate;
  106. u32 mult;
  107. mult = readl(pll->base + PLLM) & pll->pllm_mask;
  108. rate *= mult + 1;
  109. return rate;
  110. }
  111. static int davinci_pll_determine_rate(struct clk_hw *hw,
  112. struct clk_rate_request *req)
  113. {
  114. struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
  115. struct clk_hw *parent = req->best_parent_hw;
  116. unsigned long parent_rate = req->best_parent_rate;
  117. unsigned long rate = req->rate;
  118. unsigned long best_rate, r;
  119. u32 mult;
  120. /* there is a limited range of valid outputs (see datasheet) */
  121. if (rate < req->min_rate)
  122. return -EINVAL;
  123. rate = min(rate, req->max_rate);
  124. mult = rate / parent_rate;
  125. best_rate = parent_rate * mult;
  126. /* easy case when there is no PREDIV */
  127. if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
  128. if (best_rate < req->min_rate)
  129. return -EINVAL;
  130. if (mult < pll->pllm_min || mult > pll->pllm_max)
  131. return -EINVAL;
  132. req->rate = best_rate;
  133. return 0;
  134. }
  135. /* see if the PREDIV clock can help us */
  136. best_rate = 0;
  137. for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) {
  138. parent_rate = clk_hw_round_rate(parent, rate / mult);
  139. r = parent_rate * mult;
  140. if (r < req->min_rate)
  141. continue;
  142. if (r > rate || r > req->max_rate)
  143. break;
  144. if (r > best_rate) {
  145. best_rate = r;
  146. req->rate = best_rate;
  147. req->best_parent_rate = parent_rate;
  148. if (best_rate == rate)
  149. break;
  150. }
  151. }
  152. return 0;
  153. }
  154. static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  155. unsigned long parent_rate)
  156. {
  157. struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
  158. u32 mult;
  159. mult = rate / parent_rate;
  160. writel(mult - 1, pll->base + PLLM);
  161. return 0;
  162. }
  163. #ifdef CONFIG_DEBUG_FS
  164. static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
  165. #else
  166. #define davinci_pll_debug_init NULL
  167. #endif
  168. static const struct clk_ops davinci_pll_ops = {
  169. .recalc_rate = davinci_pll_recalc_rate,
  170. .determine_rate = davinci_pll_determine_rate,
  171. .set_rate = davinci_pll_set_rate,
  172. .debug_init = davinci_pll_debug_init,
  173. };
  174. /* PLLM works differently on DM365 */
  175. static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw,
  176. unsigned long parent_rate)
  177. {
  178. struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
  179. unsigned long rate = parent_rate;
  180. u32 mult;
  181. mult = readl(pll->base + PLLM) & pll->pllm_mask;
  182. rate *= mult * 2;
  183. return rate;
  184. }
  185. static const struct clk_ops dm365_pll_ops = {
  186. .recalc_rate = dm365_pll_recalc_rate,
  187. .debug_init = davinci_pll_debug_init,
  188. };
  189. /**
  190. * davinci_pll_div_register - common *DIV clock implementation
  191. * @dev: The PLL platform device or NULL
  192. * @name: the clock name
  193. * @parent_name: the parent clock name
  194. * @reg: the *DIV register
  195. * @fixed: if true, the divider is a fixed value
  196. * @flags: bitmap of CLK_* flags from clock-provider.h
  197. */
  198. static struct clk *davinci_pll_div_register(struct device *dev,
  199. const char *name,
  200. const char *parent_name,
  201. void __iomem *reg,
  202. bool fixed, u32 flags)
  203. {
  204. const char * const *parent_names = parent_name ? &parent_name : NULL;
  205. int num_parents = parent_name ? 1 : 0;
  206. const struct clk_ops *divider_ops = &clk_divider_ops;
  207. struct clk_gate *gate;
  208. struct clk_divider *divider;
  209. struct clk *clk;
  210. int ret;
  211. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  212. if (!gate)
  213. return ERR_PTR(-ENOMEM);
  214. gate->reg = reg;
  215. gate->bit_idx = DIV_ENABLE_SHIFT;
  216. divider = kzalloc(sizeof(*divider), GFP_KERNEL);
  217. if (!divider) {
  218. ret = -ENOMEM;
  219. goto err_free_gate;
  220. }
  221. divider->reg = reg;
  222. divider->shift = DIV_RATIO_SHIFT;
  223. divider->width = DIV_RATIO_WIDTH;
  224. if (fixed) {
  225. divider->flags |= CLK_DIVIDER_READ_ONLY;
  226. divider_ops = &clk_divider_ro_ops;
  227. }
  228. clk = clk_register_composite(dev, name, parent_names, num_parents,
  229. NULL, NULL, &divider->hw, divider_ops,
  230. &gate->hw, &clk_gate_ops, flags);
  231. if (IS_ERR(clk)) {
  232. ret = PTR_ERR(clk);
  233. goto err_free_divider;
  234. }
  235. return clk;
  236. err_free_divider:
  237. kfree(divider);
  238. err_free_gate:
  239. kfree(gate);
  240. return ERR_PTR(ret);
  241. }
  242. struct davinci_pllen_clk {
  243. struct clk_hw hw;
  244. void __iomem *base;
  245. };
  246. #define to_davinci_pllen_clk(_hw) \
  247. container_of((_hw), struct davinci_pllen_clk, hw)
  248. static const struct clk_ops davinci_pllen_ops = {
  249. /* this clocks just uses the clock notification feature */
  250. };
  251. /*
  252. * The PLL has to be switched into bypass mode while we are chaning the rate,
  253. * so we do that on the PLLEN clock since it is the end of the line. This will
  254. * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are
  255. * changed and will switch back to the PLL after the changes have been made.
  256. */
  257. static int davinci_pllen_rate_change(struct notifier_block *nb,
  258. unsigned long flags, void *data)
  259. {
  260. struct clk_notifier_data *cnd = data;
  261. struct clk_hw *hw = __clk_get_hw(cnd->clk);
  262. struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
  263. u32 ctrl;
  264. ctrl = readl(pll->base + PLLCTL);
  265. if (flags == PRE_RATE_CHANGE) {
  266. /* Switch the PLL to bypass mode */
  267. ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
  268. writel(ctrl, pll->base + PLLCTL);
  269. udelay(PLL_BYPASS_TIME);
  270. /* Reset and enable PLL */
  271. ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
  272. writel(ctrl, pll->base + PLLCTL);
  273. } else {
  274. udelay(PLL_RESET_TIME);
  275. /* Bring PLL out of reset */
  276. ctrl |= PLLCTL_PLLRST;
  277. writel(ctrl, pll->base + PLLCTL);
  278. udelay(PLL_LOCK_TIME);
  279. /* Remove PLL from bypass mode */
  280. ctrl |= PLLCTL_PLLEN;
  281. writel(ctrl, pll->base + PLLCTL);
  282. }
  283. return NOTIFY_OK;
  284. }
  285. static struct notifier_block davinci_pllen_notifier = {
  286. .notifier_call = davinci_pllen_rate_change,
  287. };
  288. /**
  289. * davinci_pll_clk_register - Register a PLL clock
  290. * @dev: The PLL platform device or NULL
  291. * @info: The device-specific clock info
  292. * @parent_name: The parent clock name
  293. * @base: The PLL's memory region
  294. * @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL
  295. *
  296. * This creates a series of clocks that represent the PLL.
  297. *
  298. * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN
  299. *
  300. * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL)
  301. * - PREDIV and POSTDIV are optional (depends on the PLL controller)
  302. * - PLL is the PLL output (aka PLLOUT)
  303. * - PLLEN is the bypass multiplexer
  304. *
  305. * Returns: The PLLOUT clock or a negative error code.
  306. */
  307. struct clk *davinci_pll_clk_register(struct device *dev,
  308. const struct davinci_pll_clk_info *info,
  309. const char *parent_name,
  310. void __iomem *base,
  311. struct regmap *cfgchip)
  312. {
  313. char prediv_name[MAX_NAME_SIZE];
  314. char pllout_name[MAX_NAME_SIZE];
  315. char postdiv_name[MAX_NAME_SIZE];
  316. char pllen_name[MAX_NAME_SIZE];
  317. struct clk_init_data init;
  318. struct davinci_pll_clk *pllout;
  319. struct davinci_pllen_clk *pllen;
  320. struct clk *oscin_clk = NULL;
  321. struct clk *prediv_clk = NULL;
  322. struct clk *pllout_clk;
  323. struct clk *postdiv_clk = NULL;
  324. struct clk *pllen_clk;
  325. int ret;
  326. if (info->flags & PLL_HAS_CLKMODE) {
  327. /*
  328. * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL.
  329. * We register a clock named "oscin" that serves as the internal
  330. * "input clock" domain shared by both PLLs (if there are 2)
  331. * and will be the parent clock to the AUXCLK, SYSCLKBP and
  332. * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean
  333. * a number of different things. In this driver we use it to
  334. * mean the signal after the PLLCTL[CLKMODE] switch.
  335. */
  336. oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
  337. parent_name, 0, 1, 1);
  338. if (IS_ERR(oscin_clk))
  339. return oscin_clk;
  340. parent_name = OSCIN_CLK_NAME;
  341. }
  342. if (info->flags & PLL_HAS_PREDIV) {
  343. bool fixed = info->flags & PLL_PREDIV_FIXED_DIV;
  344. u32 flags = 0;
  345. snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name);
  346. if (info->flags & PLL_PREDIV_ALWAYS_ENABLED)
  347. flags |= CLK_IS_CRITICAL;
  348. /* Some? DM355 chips don't correctly report the PREDIV value */
  349. if (info->flags & PLL_PREDIV_FIXED8)
  350. prediv_clk = clk_register_fixed_factor(dev, prediv_name,
  351. parent_name, flags, 1, 8);
  352. else
  353. prediv_clk = davinci_pll_div_register(dev, prediv_name,
  354. parent_name, base + PREDIV, fixed, flags);
  355. if (IS_ERR(prediv_clk)) {
  356. ret = PTR_ERR(prediv_clk);
  357. goto err_unregister_oscin;
  358. }
  359. parent_name = prediv_name;
  360. }
  361. /* Unlock writing to PLL registers */
  362. if (info->unlock_reg) {
  363. if (IS_ERR_OR_NULL(cfgchip))
  364. dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
  365. PTR_ERR(cfgchip));
  366. else
  367. regmap_write_bits(cfgchip, info->unlock_reg,
  368. info->unlock_mask, 0);
  369. }
  370. pllout = kzalloc(sizeof(*pllout), GFP_KERNEL);
  371. if (!pllout) {
  372. ret = -ENOMEM;
  373. goto err_unregister_prediv;
  374. }
  375. snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
  376. init.name = pllout_name;
  377. if (info->flags & PLL_PLLM_2X)
  378. init.ops = &dm365_pll_ops;
  379. else
  380. init.ops = &davinci_pll_ops;
  381. init.parent_names = &parent_name;
  382. init.num_parents = 1;
  383. init.flags = 0;
  384. if (info->flags & PLL_HAS_PREDIV)
  385. init.flags |= CLK_SET_RATE_PARENT;
  386. pllout->hw.init = &init;
  387. pllout->base = base;
  388. pllout->pllm_mask = info->pllm_mask;
  389. pllout->pllm_min = info->pllm_min;
  390. pllout->pllm_max = info->pllm_max;
  391. pllout_clk = clk_register(dev, &pllout->hw);
  392. if (IS_ERR(pllout_clk)) {
  393. ret = PTR_ERR(pllout_clk);
  394. goto err_free_pllout;
  395. }
  396. clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
  397. info->pllout_max_rate);
  398. parent_name = pllout_name;
  399. if (info->flags & PLL_HAS_POSTDIV) {
  400. bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV;
  401. u32 flags = CLK_SET_RATE_PARENT;
  402. snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name);
  403. if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
  404. flags |= CLK_IS_CRITICAL;
  405. postdiv_clk = davinci_pll_div_register(dev, postdiv_name,
  406. parent_name, base + POSTDIV, fixed, flags);
  407. if (IS_ERR(postdiv_clk)) {
  408. ret = PTR_ERR(postdiv_clk);
  409. goto err_unregister_pllout;
  410. }
  411. parent_name = postdiv_name;
  412. }
  413. pllen = kzalloc(sizeof(*pllen), GFP_KERNEL);
  414. if (!pllen) {
  415. ret = -ENOMEM;
  416. goto err_unregister_postdiv;
  417. }
  418. snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
  419. init.name = pllen_name;
  420. init.ops = &davinci_pllen_ops;
  421. init.parent_names = &parent_name;
  422. init.num_parents = 1;
  423. init.flags = CLK_SET_RATE_PARENT;
  424. pllen->hw.init = &init;
  425. pllen->base = base;
  426. pllen_clk = clk_register(dev, &pllen->hw);
  427. if (IS_ERR(pllen_clk)) {
  428. ret = PTR_ERR(pllen_clk);
  429. goto err_free_pllen;
  430. }
  431. clk_notifier_register(pllen_clk, &davinci_pllen_notifier);
  432. return pllout_clk;
  433. err_free_pllen:
  434. kfree(pllen);
  435. err_unregister_postdiv:
  436. clk_unregister(postdiv_clk);
  437. err_unregister_pllout:
  438. clk_unregister(pllout_clk);
  439. err_free_pllout:
  440. kfree(pllout);
  441. err_unregister_prediv:
  442. clk_unregister(prediv_clk);
  443. err_unregister_oscin:
  444. clk_unregister(oscin_clk);
  445. return ERR_PTR(ret);
  446. }
  447. /**
  448. * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
  449. * @dev: The PLL platform device or NULL
  450. * @name: The clock name
  451. * @base: The PLL memory region
  452. */
  453. struct clk *davinci_pll_auxclk_register(struct device *dev,
  454. const char *name,
  455. void __iomem *base)
  456. {
  457. return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN,
  458. CKEN_AUXEN_SHIFT, 0, NULL);
  459. }
  460. /**
  461. * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
  462. * @dev: The PLL platform device or NULL
  463. * @name: The clock name
  464. * @base: The PLL memory region
  465. */
  466. struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
  467. const char *name,
  468. void __iomem *base)
  469. {
  470. return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
  471. DIV_RATIO_SHIFT, DIV_RATIO_WIDTH,
  472. CLK_DIVIDER_READ_ONLY, NULL);
  473. }
  474. /**
  475. * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
  476. * @dev: The PLL platform device or NULL
  477. * @info: The clock info
  478. * @base: The PLL memory region
  479. */
  480. struct clk *
  481. davinci_pll_obsclk_register(struct device *dev,
  482. const struct davinci_pll_obsclk_info *info,
  483. void __iomem *base)
  484. {
  485. struct clk_mux *mux;
  486. struct clk_gate *gate;
  487. struct clk_divider *divider;
  488. struct clk *clk;
  489. u32 oscdiv;
  490. int ret;
  491. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  492. if (!mux)
  493. return ERR_PTR(-ENOMEM);
  494. mux->reg = base + OCSEL;
  495. mux->table = info->table;
  496. mux->mask = info->ocsrc_mask;
  497. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  498. if (!gate) {
  499. ret = -ENOMEM;
  500. goto err_free_mux;
  501. }
  502. gate->reg = base + CKEN;
  503. gate->bit_idx = CKEN_OBSCLK_SHIFT;
  504. divider = kzalloc(sizeof(*divider), GFP_KERNEL);
  505. if (!divider) {
  506. ret = -ENOMEM;
  507. goto err_free_gate;
  508. }
  509. divider->reg = base + OSCDIV;
  510. divider->shift = DIV_RATIO_SHIFT;
  511. divider->width = DIV_RATIO_WIDTH;
  512. /* make sure divider is enabled just in case bootloader disabled it */
  513. oscdiv = readl(base + OSCDIV);
  514. oscdiv |= BIT(DIV_ENABLE_SHIFT);
  515. writel(oscdiv, base + OSCDIV);
  516. clk = clk_register_composite(dev, info->name, info->parent_names,
  517. info->num_parents,
  518. &mux->hw, &clk_mux_ops,
  519. &divider->hw, &clk_divider_ops,
  520. &gate->hw, &clk_gate_ops, 0);
  521. if (IS_ERR(clk)) {
  522. ret = PTR_ERR(clk);
  523. goto err_free_divider;
  524. }
  525. return clk;
  526. err_free_divider:
  527. kfree(divider);
  528. err_free_gate:
  529. kfree(gate);
  530. err_free_mux:
  531. kfree(mux);
  532. return ERR_PTR(ret);
  533. }
  534. /* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
  535. static int davinci_pll_sysclk_rate_change(struct notifier_block *nb,
  536. unsigned long flags, void *data)
  537. {
  538. struct clk_notifier_data *cnd = data;
  539. struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk));
  540. struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
  541. u32 pllcmd, pllstat;
  542. switch (flags) {
  543. case POST_RATE_CHANGE:
  544. /* apply the changes */
  545. pllcmd = readl(pll->base + PLLCMD);
  546. pllcmd |= PLLCMD_GOSET;
  547. writel(pllcmd, pll->base + PLLCMD);
  548. fallthrough;
  549. case PRE_RATE_CHANGE:
  550. /* Wait until for outstanding changes to take effect */
  551. do {
  552. pllstat = readl(pll->base + PLLSTAT);
  553. } while (pllstat & PLLSTAT_GOSTAT);
  554. break;
  555. }
  556. return NOTIFY_OK;
  557. }
  558. static struct notifier_block davinci_pll_sysclk_notifier = {
  559. .notifier_call = davinci_pll_sysclk_rate_change,
  560. };
  561. /**
  562. * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
  563. * @dev: The PLL platform device or NULL
  564. * @info: The clock info
  565. * @base: The PLL memory region
  566. */
  567. struct clk *
  568. davinci_pll_sysclk_register(struct device *dev,
  569. const struct davinci_pll_sysclk_info *info,
  570. void __iomem *base)
  571. {
  572. const struct clk_ops *divider_ops = &clk_divider_ops;
  573. struct clk_gate *gate;
  574. struct clk_divider *divider;
  575. struct clk *clk;
  576. u32 reg;
  577. u32 flags = 0;
  578. int ret;
  579. /* PLLDIVn registers are not entirely consecutive */
  580. if (info->id < 4)
  581. reg = PLLDIV1 + 4 * (info->id - 1);
  582. else
  583. reg = PLLDIV4 + 4 * (info->id - 4);
  584. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  585. if (!gate)
  586. return ERR_PTR(-ENOMEM);
  587. gate->reg = base + reg;
  588. gate->bit_idx = DIV_ENABLE_SHIFT;
  589. divider = kzalloc(sizeof(*divider), GFP_KERNEL);
  590. if (!divider) {
  591. ret = -ENOMEM;
  592. goto err_free_gate;
  593. }
  594. divider->reg = base + reg;
  595. divider->shift = DIV_RATIO_SHIFT;
  596. divider->width = info->ratio_width;
  597. divider->flags = 0;
  598. if (info->flags & SYSCLK_FIXED_DIV) {
  599. divider->flags |= CLK_DIVIDER_READ_ONLY;
  600. divider_ops = &clk_divider_ro_ops;
  601. }
  602. /* Only the ARM clock can change the parent PLL rate */
  603. if (info->flags & SYSCLK_ARM_RATE)
  604. flags |= CLK_SET_RATE_PARENT;
  605. if (info->flags & SYSCLK_ALWAYS_ENABLED)
  606. flags |= CLK_IS_CRITICAL;
  607. clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
  608. NULL, NULL, &divider->hw, divider_ops,
  609. &gate->hw, &clk_gate_ops, flags);
  610. if (IS_ERR(clk)) {
  611. ret = PTR_ERR(clk);
  612. goto err_free_divider;
  613. }
  614. clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
  615. return clk;
  616. err_free_divider:
  617. kfree(divider);
  618. err_free_gate:
  619. kfree(gate);
  620. return ERR_PTR(ret);
  621. }
  622. int of_davinci_pll_init(struct device *dev, struct device_node *node,
  623. const struct davinci_pll_clk_info *info,
  624. const struct davinci_pll_obsclk_info *obsclk_info,
  625. const struct davinci_pll_sysclk_info **div_info,
  626. u8 max_sysclk_id,
  627. void __iomem *base,
  628. struct regmap *cfgchip)
  629. {
  630. struct device_node *child;
  631. const char *parent_name;
  632. struct clk *clk;
  633. if (info->flags & PLL_HAS_CLKMODE)
  634. parent_name = of_clk_get_parent_name(node, 0);
  635. else
  636. parent_name = OSCIN_CLK_NAME;
  637. clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
  638. if (IS_ERR(clk)) {
  639. dev_err(dev, "failed to register %s\n", info->name);
  640. return PTR_ERR(clk);
  641. }
  642. child = of_get_child_by_name(node, "pllout");
  643. if (of_device_is_available(child))
  644. of_clk_add_provider(child, of_clk_src_simple_get, clk);
  645. of_node_put(child);
  646. child = of_get_child_by_name(node, "sysclk");
  647. if (of_device_is_available(child)) {
  648. struct clk_onecell_data *clk_data;
  649. struct clk **clks;
  650. int n_clks = max_sysclk_id + 1;
  651. int i;
  652. clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  653. if (!clk_data) {
  654. of_node_put(child);
  655. return -ENOMEM;
  656. }
  657. clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
  658. if (!clks) {
  659. kfree(clk_data);
  660. of_node_put(child);
  661. return -ENOMEM;
  662. }
  663. clk_data->clks = clks;
  664. clk_data->clk_num = n_clks;
  665. for (i = 0; i < n_clks; i++)
  666. clks[i] = ERR_PTR(-ENOENT);
  667. for (; *div_info; div_info++) {
  668. clk = davinci_pll_sysclk_register(dev, *div_info, base);
  669. if (IS_ERR(clk))
  670. dev_warn(dev, "failed to register %s (%ld)\n",
  671. (*div_info)->name, PTR_ERR(clk));
  672. else
  673. clks[(*div_info)->id] = clk;
  674. }
  675. of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
  676. }
  677. of_node_put(child);
  678. child = of_get_child_by_name(node, "auxclk");
  679. if (of_device_is_available(child)) {
  680. char child_name[MAX_NAME_SIZE];
  681. snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name);
  682. clk = davinci_pll_auxclk_register(dev, child_name, base);
  683. if (IS_ERR(clk))
  684. dev_warn(dev, "failed to register %s (%ld)\n",
  685. child_name, PTR_ERR(clk));
  686. else
  687. of_clk_add_provider(child, of_clk_src_simple_get, clk);
  688. }
  689. of_node_put(child);
  690. child = of_get_child_by_name(node, "obsclk");
  691. if (of_device_is_available(child)) {
  692. if (obsclk_info)
  693. clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
  694. else
  695. clk = ERR_PTR(-EINVAL);
  696. if (IS_ERR(clk))
  697. dev_warn(dev, "failed to register obsclk (%ld)\n",
  698. PTR_ERR(clk));
  699. else
  700. of_clk_add_provider(child, of_clk_src_simple_get, clk);
  701. }
  702. of_node_put(child);
  703. return 0;
  704. }
  705. static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
  706. {
  707. struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
  708. /*
  709. * Platform data is optional, so allocate a new struct if one was not
  710. * provided. For device tree, this will always be the case.
  711. */
  712. if (!pdata)
  713. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  714. if (!pdata)
  715. return NULL;
  716. /* for device tree, we need to fill in the struct */
  717. if (dev->of_node)
  718. pdata->cfgchip =
  719. syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
  720. return pdata;
  721. }
  722. /* needed in early boot for clocksource/clockevent */
  723. #ifdef CONFIG_ARCH_DAVINCI_DA850
  724. CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
  725. #endif
  726. static const struct of_device_id davinci_pll_of_match[] = {
  727. #ifdef CONFIG_ARCH_DAVINCI_DA850
  728. { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
  729. #endif
  730. { }
  731. };
  732. static const struct platform_device_id davinci_pll_id_table[] = {
  733. #ifdef CONFIG_ARCH_DAVINCI_DA830
  734. { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init },
  735. #endif
  736. #ifdef CONFIG_ARCH_DAVINCI_DA850
  737. { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
  738. { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
  739. #endif
  740. #ifdef CONFIG_ARCH_DAVINCI_DM355
  741. { .name = "dm355-pll1", .driver_data = (kernel_ulong_t)dm355_pll1_init },
  742. { .name = "dm355-pll2", .driver_data = (kernel_ulong_t)dm355_pll2_init },
  743. #endif
  744. #ifdef CONFIG_ARCH_DAVINCI_DM365
  745. { .name = "dm365-pll1", .driver_data = (kernel_ulong_t)dm365_pll1_init },
  746. { .name = "dm365-pll2", .driver_data = (kernel_ulong_t)dm365_pll2_init },
  747. #endif
  748. #ifdef CONFIG_ARCH_DAVINCI_DM644x
  749. { .name = "dm644x-pll1", .driver_data = (kernel_ulong_t)dm644x_pll1_init },
  750. { .name = "dm644x-pll2", .driver_data = (kernel_ulong_t)dm644x_pll2_init },
  751. #endif
  752. #ifdef CONFIG_ARCH_DAVINCI_DM646x
  753. { .name = "dm646x-pll1", .driver_data = (kernel_ulong_t)dm646x_pll1_init },
  754. { .name = "dm646x-pll2", .driver_data = (kernel_ulong_t)dm646x_pll2_init },
  755. #endif
  756. { }
  757. };
  758. typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
  759. struct regmap *cfgchip);
  760. static int davinci_pll_probe(struct platform_device *pdev)
  761. {
  762. struct device *dev = &pdev->dev;
  763. struct davinci_pll_platform_data *pdata;
  764. const struct of_device_id *of_id;
  765. davinci_pll_init pll_init = NULL;
  766. void __iomem *base;
  767. of_id = of_match_device(davinci_pll_of_match, dev);
  768. if (of_id)
  769. pll_init = of_id->data;
  770. else if (pdev->id_entry)
  771. pll_init = (void *)pdev->id_entry->driver_data;
  772. if (!pll_init) {
  773. dev_err(dev, "unable to find driver data\n");
  774. return -EINVAL;
  775. }
  776. pdata = davinci_pll_get_pdata(dev);
  777. if (!pdata) {
  778. dev_err(dev, "missing platform data\n");
  779. return -EINVAL;
  780. }
  781. base = devm_platform_ioremap_resource(pdev, 0);
  782. if (IS_ERR(base))
  783. return PTR_ERR(base);
  784. return pll_init(dev, base, pdata->cfgchip);
  785. }
  786. static struct platform_driver davinci_pll_driver = {
  787. .probe = davinci_pll_probe,
  788. .driver = {
  789. .name = "davinci-pll-clk",
  790. .of_match_table = davinci_pll_of_match,
  791. },
  792. .id_table = davinci_pll_id_table,
  793. };
  794. static int __init davinci_pll_driver_init(void)
  795. {
  796. return platform_driver_register(&davinci_pll_driver);
  797. }
  798. /* has to be postcore_initcall because PSC devices depend on PLL parent clocks */
  799. postcore_initcall(davinci_pll_driver_init);
  800. #ifdef CONFIG_DEBUG_FS
  801. #include <linux/debugfs.h>
  802. #define DEBUG_REG(n) \
  803. { \
  804. .name = #n, \
  805. .offset = n, \
  806. }
  807. static const struct debugfs_reg32 davinci_pll_regs[] = {
  808. DEBUG_REG(REVID),
  809. DEBUG_REG(PLLCTL),
  810. DEBUG_REG(OCSEL),
  811. DEBUG_REG(PLLSECCTL),
  812. DEBUG_REG(PLLM),
  813. DEBUG_REG(PREDIV),
  814. DEBUG_REG(PLLDIV1),
  815. DEBUG_REG(PLLDIV2),
  816. DEBUG_REG(PLLDIV3),
  817. DEBUG_REG(OSCDIV),
  818. DEBUG_REG(POSTDIV),
  819. DEBUG_REG(BPDIV),
  820. DEBUG_REG(PLLCMD),
  821. DEBUG_REG(PLLSTAT),
  822. DEBUG_REG(ALNCTL),
  823. DEBUG_REG(DCHANGE),
  824. DEBUG_REG(CKEN),
  825. DEBUG_REG(CKSTAT),
  826. DEBUG_REG(SYSTAT),
  827. DEBUG_REG(PLLDIV4),
  828. DEBUG_REG(PLLDIV5),
  829. DEBUG_REG(PLLDIV6),
  830. DEBUG_REG(PLLDIV7),
  831. DEBUG_REG(PLLDIV8),
  832. DEBUG_REG(PLLDIV9),
  833. };
  834. static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
  835. {
  836. struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
  837. struct debugfs_regset32 *regset;
  838. regset = kzalloc(sizeof(*regset), GFP_KERNEL);
  839. if (!regset)
  840. return;
  841. regset->regs = davinci_pll_regs;
  842. regset->nregs = ARRAY_SIZE(davinci_pll_regs);
  843. regset->base = pll->base;
  844. debugfs_create_regset32("registers", 0400, dentry, regset);
  845. }
  846. #endif