pll-dm365.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PLL clock descriptions for TI DM365
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clkdev.h>
  9. #include <linux/clk/davinci.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include "pll.h"
  14. #define OCSEL_OCSRC_ENABLE 0
  15. static const struct davinci_pll_clk_info dm365_pll1_info = {
  16. .name = "pll1",
  17. .pllm_mask = GENMASK(9, 0),
  18. .pllm_min = 1,
  19. .pllm_max = 1023,
  20. .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
  21. PLL_POSTDIV_ALWAYS_ENABLED | PLL_PLLM_2X,
  22. };
  23. SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  24. SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  25. SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  26. SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  27. SYSCLK(5, pll1_sysclk5, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  28. SYSCLK(6, pll1_sysclk6, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  29. SYSCLK(7, pll1_sysclk7, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  30. SYSCLK(8, pll1_sysclk8, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  31. SYSCLK(9, pll1_sysclk9, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  32. /*
  33. * This is a bit of a hack to make OCSEL[OCSRC] on DM365 look like OCSEL[OCSRC]
  34. * on DA850. On DM365, OCSEL[OCSRC] is just an enable/disable bit instead of a
  35. * multiplexer. By modeling it as a single parent mux clock, the clock code will
  36. * still do the right thing in this case.
  37. */
  38. static const char * const dm365_pll_obsclk_parent_names[] = {
  39. "oscin",
  40. };
  41. static u32 dm365_pll_obsclk_table[] = {
  42. OCSEL_OCSRC_ENABLE,
  43. };
  44. static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
  45. .name = "pll1_obsclk",
  46. .parent_names = dm365_pll_obsclk_parent_names,
  47. .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
  48. .table = dm365_pll_obsclk_table,
  49. .ocsrc_mask = BIT(4),
  50. };
  51. int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  52. {
  53. struct clk *clk;
  54. davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
  55. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
  56. clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
  57. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
  58. clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
  59. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
  60. clk_register_clkdev(clk, "pll1_sysclk3", "dm365-psc");
  61. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
  62. clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
  63. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
  64. clk_register_clkdev(clk, "pll1_sysclk5", "dm365-psc");
  65. davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
  66. davinci_pll_sysclk_register(dev, &pll1_sysclk7, base);
  67. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
  68. clk_register_clkdev(clk, "pll1_sysclk8", "dm365-psc");
  69. davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
  70. clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
  71. clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
  72. davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
  73. davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base);
  74. return 0;
  75. }
  76. static const struct davinci_pll_clk_info dm365_pll2_info = {
  77. .name = "pll2",
  78. .pllm_mask = GENMASK(9, 0),
  79. .pllm_min = 1,
  80. .pllm_max = 1023,
  81. .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_POSTDIV_ALWAYS_ENABLED |
  82. PLL_PLLM_2X,
  83. };
  84. SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  85. SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  86. SYSCLK(3, pll2_sysclk3, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  87. SYSCLK(4, pll2_sysclk4, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  88. SYSCLK(5, pll2_sysclk5, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  89. static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
  90. .name = "pll2_obsclk",
  91. .parent_names = dm365_pll_obsclk_parent_names,
  92. .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
  93. .table = dm365_pll_obsclk_table,
  94. .ocsrc_mask = BIT(4),
  95. };
  96. int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  97. {
  98. struct clk *clk;
  99. davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
  100. davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
  101. clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
  102. clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
  103. davinci_pll_sysclk_register(dev, &pll2_sysclk3, base);
  104. clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base);
  105. clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
  106. davinci_pll_sysclk_register(dev, &pll2_sysclk5, base);
  107. davinci_pll_auxclk_register(dev, "pll2_auxclk", base);
  108. davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base);
  109. return 0;
  110. }