pll-dm355.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PLL clock descriptions for TI DM355
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk/davinci.h>
  9. #include <linux/clkdev.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include "pll.h"
  13. static const struct davinci_pll_clk_info dm355_pll1_info = {
  14. .name = "pll1",
  15. .pllm_mask = GENMASK(7, 0),
  16. .pllm_min = 92,
  17. .pllm_max = 184,
  18. .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED |
  19. PLL_PREDIV_FIXED8 | PLL_HAS_POSTDIV |
  20. PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  21. };
  22. SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  23. SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  24. SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  25. SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  26. int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  27. {
  28. struct clk *clk;
  29. davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);
  30. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
  31. clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
  32. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
  33. clk_register_clkdev(clk, "pll1_sysclk2", "dm355-psc");
  34. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
  35. clk_register_clkdev(clk, "pll1_sysclk3", "dm355-psc");
  36. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
  37. clk_register_clkdev(clk, "pll1_sysclk4", "dm355-psc");
  38. clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
  39. clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
  40. davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
  41. return 0;
  42. }
  43. static const struct davinci_pll_clk_info dm355_pll2_info = {
  44. .name = "pll2",
  45. .pllm_mask = GENMASK(7, 0),
  46. .pllm_min = 92,
  47. .pllm_max = 184,
  48. .flags = PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED | PLL_HAS_POSTDIV |
  49. PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  50. };
  51. SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  52. int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  53. {
  54. davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);
  55. davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
  56. davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
  57. return 0;
  58. }