pll-da850.c 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/clk/davinci.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/device.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/mfd/da8xx-cfgchip.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of.h>
  19. #include <linux/types.h>
  20. #include "pll.h"
  21. #define OCSEL_OCSRC_OSCIN 0x14
  22. #define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n))
  23. #define OCSEL_OCSRC_PLL1_OBSCLK 0x1e
  24. #define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n))
  25. static const struct davinci_pll_clk_info da850_pll0_info = {
  26. .name = "pll0",
  27. .unlock_reg = CFGCHIP(0),
  28. .unlock_mask = CFGCHIP0_PLL_MASTER_LOCK,
  29. .pllm_mask = GENMASK(4, 0),
  30. .pllm_min = 4,
  31. .pllm_max = 32,
  32. .pllout_min_rate = 300000000,
  33. .pllout_max_rate = 600000000,
  34. .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
  35. PLL_HAS_EXTCLKSRC,
  36. };
  37. /*
  38. * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
  39. * meaning that we could change the divider as long as we keep the correct
  40. * ratio between all of the clocks, but we don't support that because there is
  41. * currently not a need for it.
  42. */
  43. SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
  44. SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
  45. SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
  46. SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
  47. SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
  48. SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
  49. SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
  50. static const char * const da850_pll0_obsclk_parent_names[] = {
  51. "oscin",
  52. "pll0_sysclk1",
  53. "pll0_sysclk2",
  54. "pll0_sysclk3",
  55. "pll0_sysclk4",
  56. "pll0_sysclk5",
  57. "pll0_sysclk6",
  58. "pll0_sysclk7",
  59. "pll1_obsclk",
  60. };
  61. static u32 da850_pll0_obsclk_table[] = {
  62. OCSEL_OCSRC_OSCIN,
  63. OCSEL_OCSRC_PLL0_SYSCLK(1),
  64. OCSEL_OCSRC_PLL0_SYSCLK(2),
  65. OCSEL_OCSRC_PLL0_SYSCLK(3),
  66. OCSEL_OCSRC_PLL0_SYSCLK(4),
  67. OCSEL_OCSRC_PLL0_SYSCLK(5),
  68. OCSEL_OCSRC_PLL0_SYSCLK(6),
  69. OCSEL_OCSRC_PLL0_SYSCLK(7),
  70. OCSEL_OCSRC_PLL1_OBSCLK,
  71. };
  72. static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
  73. .name = "pll0_obsclk",
  74. .parent_names = da850_pll0_obsclk_parent_names,
  75. .num_parents = ARRAY_SIZE(da850_pll0_obsclk_parent_names),
  76. .table = da850_pll0_obsclk_table,
  77. .ocsrc_mask = GENMASK(4, 0),
  78. };
  79. int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  80. {
  81. struct clk *clk;
  82. davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);
  83. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
  84. clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
  85. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
  86. clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0");
  87. clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1");
  88. clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc");
  89. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
  90. clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc");
  91. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
  92. clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0");
  93. clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1");
  94. davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
  95. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
  96. clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0");
  97. davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
  98. davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
  99. clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk",
  100. CLK_IS_CRITICAL, 1, 1);
  101. clk_register_clkdev(clk, NULL, "i2c_davinci.1");
  102. clk_register_clkdev(clk, "timer0", NULL);
  103. clk_register_clkdev(clk, NULL, "davinci-wdt");
  104. davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base);
  105. return 0;
  106. }
  107. static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
  108. &pll0_sysclk1,
  109. &pll0_sysclk2,
  110. &pll0_sysclk3,
  111. &pll0_sysclk4,
  112. &pll0_sysclk5,
  113. &pll0_sysclk6,
  114. &pll0_sysclk7,
  115. NULL
  116. };
  117. void of_da850_pll0_init(struct device_node *node)
  118. {
  119. void __iomem *base;
  120. struct regmap *cfgchip;
  121. base = of_iomap(node, 0);
  122. if (!base) {
  123. pr_err("%s: ioremap failed\n", __func__);
  124. return;
  125. }
  126. cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
  127. of_davinci_pll_init(NULL, node, &da850_pll0_info,
  128. &da850_pll0_obsclk_info,
  129. da850_pll0_sysclk_info, 7, base, cfgchip);
  130. }
  131. static const struct davinci_pll_clk_info da850_pll1_info = {
  132. .name = "pll1",
  133. .unlock_reg = CFGCHIP(3),
  134. .unlock_mask = CFGCHIP3_PLL1_MASTER_LOCK,
  135. .pllm_mask = GENMASK(4, 0),
  136. .pllm_min = 4,
  137. .pllm_max = 32,
  138. .pllout_min_rate = 300000000,
  139. .pllout_max_rate = 600000000,
  140. .flags = PLL_HAS_POSTDIV,
  141. };
  142. SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  143. SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
  144. SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
  145. static const char * const da850_pll1_obsclk_parent_names[] = {
  146. "oscin",
  147. "pll1_sysclk1",
  148. "pll1_sysclk2",
  149. "pll1_sysclk3",
  150. };
  151. static u32 da850_pll1_obsclk_table[] = {
  152. OCSEL_OCSRC_OSCIN,
  153. OCSEL_OCSRC_PLL1_SYSCLK(1),
  154. OCSEL_OCSRC_PLL1_SYSCLK(2),
  155. OCSEL_OCSRC_PLL1_SYSCLK(3),
  156. };
  157. static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
  158. .name = "pll1_obsclk",
  159. .parent_names = da850_pll1_obsclk_parent_names,
  160. .num_parents = ARRAY_SIZE(da850_pll1_obsclk_parent_names),
  161. .table = da850_pll1_obsclk_table,
  162. .ocsrc_mask = GENMASK(4, 0),
  163. };
  164. int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  165. {
  166. struct clk *clk;
  167. davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
  168. davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
  169. clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
  170. clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc");
  171. davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
  172. davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base);
  173. return 0;
  174. }
  175. static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
  176. &pll1_sysclk1,
  177. &pll1_sysclk2,
  178. &pll1_sysclk3,
  179. NULL
  180. };
  181. int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  182. {
  183. return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
  184. &da850_pll1_obsclk_info,
  185. da850_pll1_sysclk_info, 3, base, cfgchip);
  186. }