pll-da830.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/clkdev.h>
  8. #include <linux/clk/davinci.h>
  9. #include <linux/bitops.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include "pll.h"
  13. static const struct davinci_pll_clk_info da830_pll_info = {
  14. .name = "pll0",
  15. .pllm_mask = GENMASK(4, 0),
  16. .pllm_min = 4,
  17. .pllm_max = 32,
  18. .pllout_min_rate = 300000000,
  19. .pllout_max_rate = 600000000,
  20. .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  21. };
  22. /*
  23. * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
  24. * meaning that we could change the divider as long as we keep the correct
  25. * ratio between all of the clocks, but we don't support that because there is
  26. * currently not a need for it.
  27. */
  28. SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
  29. SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
  30. SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
  31. SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
  32. SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
  33. SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
  34. int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  35. {
  36. struct clk *clk;
  37. davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
  38. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
  39. clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
  40. clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
  41. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
  42. clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
  43. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
  44. clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
  45. clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
  46. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
  47. clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
  48. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
  49. clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
  50. clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
  51. clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
  52. clk_register_clkdev(clk, NULL, "i2c_davinci.1");
  53. clk_register_clkdev(clk, "timer0", NULL);
  54. clk_register_clkdev(clk, NULL, "davinci-wdt");
  55. return 0;
  56. }