da8xx-cfgchip.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
  4. *
  5. * Copyright (C) 2018 David Lechner <david@lechnology.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk.h>
  9. #include <linux/clkdev.h>
  10. #include <linux/init.h>
  11. #include <linux/mfd/da8xx-cfgchip.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_data/clk-da8xx-cfgchip.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #include <linux/slab.h>
  19. /* --- Gate clocks --- */
  20. #define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1)
  21. struct da8xx_cfgchip_gate_clk_info {
  22. const char *name;
  23. u32 cfgchip;
  24. u32 bit;
  25. u32 flags;
  26. };
  27. struct da8xx_cfgchip_gate_clk {
  28. struct clk_hw hw;
  29. struct regmap *regmap;
  30. u32 reg;
  31. u32 mask;
  32. };
  33. #define to_da8xx_cfgchip_gate_clk(_hw) \
  34. container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
  35. static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw)
  36. {
  37. struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
  38. return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask);
  39. }
  40. static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw)
  41. {
  42. struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
  43. regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0);
  44. }
  45. static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw)
  46. {
  47. struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
  48. unsigned int val;
  49. regmap_read(clk->regmap, clk->reg, &val);
  50. return !!(val & clk->mask);
  51. }
  52. static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw,
  53. unsigned long parent_rate)
  54. {
  55. /* this clock divides by 4.5 */
  56. return parent_rate * 2 / 9;
  57. }
  58. static const struct clk_ops da8xx_cfgchip_gate_clk_ops = {
  59. .enable = da8xx_cfgchip_gate_clk_enable,
  60. .disable = da8xx_cfgchip_gate_clk_disable,
  61. .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
  62. };
  63. static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = {
  64. .enable = da8xx_cfgchip_gate_clk_enable,
  65. .disable = da8xx_cfgchip_gate_clk_disable,
  66. .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
  67. .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate,
  68. };
  69. static struct da8xx_cfgchip_gate_clk * __init
  70. da8xx_cfgchip_gate_clk_register(struct device *dev,
  71. const struct da8xx_cfgchip_gate_clk_info *info,
  72. struct regmap *regmap)
  73. {
  74. struct clk *parent;
  75. const char *parent_name;
  76. struct da8xx_cfgchip_gate_clk *gate;
  77. struct clk_init_data init;
  78. int ret;
  79. parent = devm_clk_get(dev, NULL);
  80. if (IS_ERR(parent))
  81. return ERR_CAST(parent);
  82. parent_name = __clk_get_name(parent);
  83. gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
  84. if (!gate)
  85. return ERR_PTR(-ENOMEM);
  86. init.name = info->name;
  87. if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5)
  88. init.ops = &da8xx_cfgchip_div4p5_clk_ops;
  89. else
  90. init.ops = &da8xx_cfgchip_gate_clk_ops;
  91. init.parent_names = &parent_name;
  92. init.num_parents = 1;
  93. init.flags = 0;
  94. gate->hw.init = &init;
  95. gate->regmap = regmap;
  96. gate->reg = info->cfgchip;
  97. gate->mask = info->bit;
  98. ret = devm_clk_hw_register(dev, &gate->hw);
  99. if (ret < 0)
  100. return ERR_PTR(ret);
  101. return gate;
  102. }
  103. static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
  104. .name = "ehrpwm_tbclk",
  105. .cfgchip = CFGCHIP(1),
  106. .bit = CFGCHIP1_TBCLKSYNC,
  107. };
  108. static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
  109. struct regmap *regmap)
  110. {
  111. struct da8xx_cfgchip_gate_clk *gate;
  112. gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
  113. regmap);
  114. if (IS_ERR(gate))
  115. return PTR_ERR(gate);
  116. clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
  117. clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
  118. return 0;
  119. }
  120. static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = {
  121. .name = "div4.5",
  122. .cfgchip = CFGCHIP(3),
  123. .bit = CFGCHIP3_DIV45PENA,
  124. .flags = DA8XX_GATE_CLOCK_IS_DIV4P5,
  125. };
  126. static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
  127. struct regmap *regmap)
  128. {
  129. struct da8xx_cfgchip_gate_clk *gate;
  130. gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
  131. return PTR_ERR_OR_ZERO(gate);
  132. }
  133. static int __init
  134. of_da8xx_cfgchip_gate_clk_init(struct device *dev,
  135. const struct da8xx_cfgchip_gate_clk_info *info,
  136. struct regmap *regmap)
  137. {
  138. struct da8xx_cfgchip_gate_clk *gate;
  139. gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap);
  140. if (IS_ERR(gate))
  141. return PTR_ERR(gate);
  142. return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate);
  143. }
  144. static int __init of_da8xx_tbclksync_init(struct device *dev,
  145. struct regmap *regmap)
  146. {
  147. return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap);
  148. }
  149. static int __init of_da8xx_div4p5ena_init(struct device *dev,
  150. struct regmap *regmap)
  151. {
  152. return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap);
  153. }
  154. /* --- MUX clocks --- */
  155. struct da8xx_cfgchip_mux_clk_info {
  156. const char *name;
  157. const char *parent0;
  158. const char *parent1;
  159. u32 cfgchip;
  160. u32 bit;
  161. };
  162. struct da8xx_cfgchip_mux_clk {
  163. struct clk_hw hw;
  164. struct regmap *regmap;
  165. u32 reg;
  166. u32 mask;
  167. };
  168. #define to_da8xx_cfgchip_mux_clk(_hw) \
  169. container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
  170. static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index)
  171. {
  172. struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
  173. unsigned int val = index ? clk->mask : 0;
  174. return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val);
  175. }
  176. static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
  177. {
  178. struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
  179. unsigned int val;
  180. regmap_read(clk->regmap, clk->reg, &val);
  181. return (val & clk->mask) ? 1 : 0;
  182. }
  183. static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
  184. .set_parent = da8xx_cfgchip_mux_clk_set_parent,
  185. .get_parent = da8xx_cfgchip_mux_clk_get_parent,
  186. };
  187. static struct da8xx_cfgchip_mux_clk * __init
  188. da8xx_cfgchip_mux_clk_register(struct device *dev,
  189. const struct da8xx_cfgchip_mux_clk_info *info,
  190. struct regmap *regmap)
  191. {
  192. const char * const parent_names[] = { info->parent0, info->parent1 };
  193. struct da8xx_cfgchip_mux_clk *mux;
  194. struct clk_init_data init;
  195. int ret;
  196. mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
  197. if (!mux)
  198. return ERR_PTR(-ENOMEM);
  199. init.name = info->name;
  200. init.ops = &da8xx_cfgchip_mux_clk_ops;
  201. init.parent_names = parent_names;
  202. init.num_parents = 2;
  203. init.flags = 0;
  204. mux->hw.init = &init;
  205. mux->regmap = regmap;
  206. mux->reg = info->cfgchip;
  207. mux->mask = info->bit;
  208. ret = devm_clk_hw_register(dev, &mux->hw);
  209. if (ret < 0)
  210. return ERR_PTR(ret);
  211. return mux;
  212. }
  213. static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = {
  214. .name = "async1",
  215. .parent0 = "pll0_sysclk3",
  216. .parent1 = "div4.5",
  217. .cfgchip = CFGCHIP(3),
  218. .bit = CFGCHIP3_EMA_CLKSRC,
  219. };
  220. static int __init da8xx_cfgchip_register_async1(struct device *dev,
  221. struct regmap *regmap)
  222. {
  223. struct da8xx_cfgchip_mux_clk *mux;
  224. mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap);
  225. if (IS_ERR(mux))
  226. return PTR_ERR(mux);
  227. clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0");
  228. return 0;
  229. }
  230. static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = {
  231. .name = "async3",
  232. .parent0 = "pll0_sysclk2",
  233. .parent1 = "pll1_sysclk2",
  234. .cfgchip = CFGCHIP(3),
  235. .bit = CFGCHIP3_ASYNC3_CLKSRC,
  236. };
  237. static int __init da850_cfgchip_register_async3(struct device *dev,
  238. struct regmap *regmap)
  239. {
  240. struct da8xx_cfgchip_mux_clk *mux;
  241. struct clk_hw *parent;
  242. mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap);
  243. if (IS_ERR(mux))
  244. return PTR_ERR(mux);
  245. clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1");
  246. /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
  247. parent = clk_hw_get_parent_by_index(&mux->hw, 1);
  248. if (parent)
  249. clk_set_parent(mux->hw.clk, parent->clk);
  250. else
  251. dev_warn(dev, "Failed to find async3 parent clock\n");
  252. return 0;
  253. }
  254. static int __init
  255. of_da8xx_cfgchip_init_mux_clock(struct device *dev,
  256. const struct da8xx_cfgchip_mux_clk_info *info,
  257. struct regmap *regmap)
  258. {
  259. struct da8xx_cfgchip_mux_clk *mux;
  260. mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap);
  261. if (IS_ERR(mux))
  262. return PTR_ERR(mux);
  263. return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw);
  264. }
  265. static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap)
  266. {
  267. return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap);
  268. }
  269. static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap)
  270. {
  271. return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
  272. }
  273. /* --- USB 2.0 PHY clock --- */
  274. struct da8xx_usb0_clk48 {
  275. struct clk_hw hw;
  276. struct clk *fck;
  277. struct regmap *regmap;
  278. };
  279. #define to_da8xx_usb0_clk48(_hw) \
  280. container_of((_hw), struct da8xx_usb0_clk48, hw)
  281. static int da8xx_usb0_clk48_prepare(struct clk_hw *hw)
  282. {
  283. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  284. /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0
  285. * PHY clock enable, but since clk_prepare() can't be called in an
  286. * atomic context (i.e. in clk_enable()), we have to prepare it here.
  287. */
  288. return clk_prepare(usb0->fck);
  289. }
  290. static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw)
  291. {
  292. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  293. clk_unprepare(usb0->fck);
  294. }
  295. static int da8xx_usb0_clk48_enable(struct clk_hw *hw)
  296. {
  297. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  298. unsigned int mask, val;
  299. int ret;
  300. /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled
  301. * temporaily. It can be turned back off once the PLL is locked.
  302. */
  303. clk_enable(usb0->fck);
  304. /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
  305. * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used.
  306. */
  307. mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
  308. val = CFGCHIP2_PHY_PLLON;
  309. regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
  310. ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val,
  311. val & CFGCHIP2_PHYCLKGD, 0, 500000);
  312. clk_disable(usb0->fck);
  313. return ret;
  314. }
  315. static void da8xx_usb0_clk48_disable(struct clk_hw *hw)
  316. {
  317. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  318. unsigned int val;
  319. val = CFGCHIP2_PHYPWRDN;
  320. regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val);
  321. }
  322. static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw)
  323. {
  324. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  325. unsigned int val;
  326. regmap_read(usb0->regmap, CFGCHIP(2), &val);
  327. return !!(val & CFGCHIP2_PHYCLKGD);
  328. }
  329. static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
  330. unsigned long parent_rate)
  331. {
  332. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  333. unsigned int mask, val;
  334. /* The parent clock rate must be one of the following */
  335. mask = CFGCHIP2_REFFREQ_MASK;
  336. switch (parent_rate) {
  337. case 12000000:
  338. val = CFGCHIP2_REFFREQ_12MHZ;
  339. break;
  340. case 13000000:
  341. val = CFGCHIP2_REFFREQ_13MHZ;
  342. break;
  343. case 19200000:
  344. val = CFGCHIP2_REFFREQ_19_2MHZ;
  345. break;
  346. case 20000000:
  347. val = CFGCHIP2_REFFREQ_20MHZ;
  348. break;
  349. case 24000000:
  350. val = CFGCHIP2_REFFREQ_24MHZ;
  351. break;
  352. case 26000000:
  353. val = CFGCHIP2_REFFREQ_26MHZ;
  354. break;
  355. case 38400000:
  356. val = CFGCHIP2_REFFREQ_38_4MHZ;
  357. break;
  358. case 40000000:
  359. val = CFGCHIP2_REFFREQ_40MHZ;
  360. break;
  361. case 48000000:
  362. val = CFGCHIP2_REFFREQ_48MHZ;
  363. break;
  364. default:
  365. return 0;
  366. }
  367. regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
  368. /* USB 2.0 PLL always supplies 48MHz */
  369. return 48000000;
  370. }
  371. static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
  372. unsigned long *parent_rate)
  373. {
  374. return 48000000;
  375. }
  376. static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
  377. {
  378. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  379. return regmap_write_bits(usb0->regmap, CFGCHIP(2),
  380. CFGCHIP2_USB2PHYCLKMUX,
  381. index ? CFGCHIP2_USB2PHYCLKMUX : 0);
  382. }
  383. static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw)
  384. {
  385. struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
  386. unsigned int val;
  387. regmap_read(usb0->regmap, CFGCHIP(2), &val);
  388. return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0;
  389. }
  390. static const struct clk_ops da8xx_usb0_clk48_ops = {
  391. .prepare = da8xx_usb0_clk48_prepare,
  392. .unprepare = da8xx_usb0_clk48_unprepare,
  393. .enable = da8xx_usb0_clk48_enable,
  394. .disable = da8xx_usb0_clk48_disable,
  395. .is_enabled = da8xx_usb0_clk48_is_enabled,
  396. .recalc_rate = da8xx_usb0_clk48_recalc_rate,
  397. .round_rate = da8xx_usb0_clk48_round_rate,
  398. .set_parent = da8xx_usb0_clk48_set_parent,
  399. .get_parent = da8xx_usb0_clk48_get_parent,
  400. };
  401. static struct da8xx_usb0_clk48 *
  402. da8xx_cfgchip_register_usb0_clk48(struct device *dev,
  403. struct regmap *regmap)
  404. {
  405. const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
  406. struct clk *fck_clk;
  407. struct da8xx_usb0_clk48 *usb0;
  408. struct clk_init_data init;
  409. int ret;
  410. fck_clk = devm_clk_get(dev, "fck");
  411. if (IS_ERR(fck_clk)) {
  412. if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
  413. dev_err(dev, "Missing fck clock\n");
  414. return ERR_CAST(fck_clk);
  415. }
  416. usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
  417. if (!usb0)
  418. return ERR_PTR(-ENOMEM);
  419. init.name = "usb0_clk48";
  420. init.ops = &da8xx_usb0_clk48_ops;
  421. init.parent_names = parent_names;
  422. init.num_parents = 2;
  423. usb0->hw.init = &init;
  424. usb0->fck = fck_clk;
  425. usb0->regmap = regmap;
  426. ret = devm_clk_hw_register(dev, &usb0->hw);
  427. if (ret < 0)
  428. return ERR_PTR(ret);
  429. return usb0;
  430. }
  431. /* --- USB 1.1 PHY clock --- */
  432. struct da8xx_usb1_clk48 {
  433. struct clk_hw hw;
  434. struct regmap *regmap;
  435. };
  436. #define to_da8xx_usb1_clk48(_hw) \
  437. container_of((_hw), struct da8xx_usb1_clk48, hw)
  438. static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index)
  439. {
  440. struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
  441. return regmap_write_bits(usb1->regmap, CFGCHIP(2),
  442. CFGCHIP2_USB1PHYCLKMUX,
  443. index ? CFGCHIP2_USB1PHYCLKMUX : 0);
  444. }
  445. static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
  446. {
  447. struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
  448. unsigned int val;
  449. regmap_read(usb1->regmap, CFGCHIP(2), &val);
  450. return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0;
  451. }
  452. static const struct clk_ops da8xx_usb1_clk48_ops = {
  453. .set_parent = da8xx_usb1_clk48_set_parent,
  454. .get_parent = da8xx_usb1_clk48_get_parent,
  455. };
  456. /**
  457. * da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
  458. * @dev: The device
  459. * @regmap: The CFGCHIP regmap
  460. */
  461. static struct da8xx_usb1_clk48 *
  462. da8xx_cfgchip_register_usb1_clk48(struct device *dev,
  463. struct regmap *regmap)
  464. {
  465. const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
  466. struct da8xx_usb1_clk48 *usb1;
  467. struct clk_init_data init;
  468. int ret;
  469. usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
  470. if (!usb1)
  471. return ERR_PTR(-ENOMEM);
  472. init.name = "usb1_clk48";
  473. init.ops = &da8xx_usb1_clk48_ops;
  474. init.parent_names = parent_names;
  475. init.num_parents = 2;
  476. usb1->hw.init = &init;
  477. usb1->regmap = regmap;
  478. ret = devm_clk_hw_register(dev, &usb1->hw);
  479. if (ret < 0)
  480. return ERR_PTR(ret);
  481. return usb1;
  482. }
  483. static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev,
  484. struct regmap *regmap)
  485. {
  486. struct da8xx_usb0_clk48 *usb0;
  487. struct da8xx_usb1_clk48 *usb1;
  488. struct clk_hw *parent;
  489. usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
  490. if (IS_ERR(usb0))
  491. return PTR_ERR(usb0);
  492. /*
  493. * All existing boards use pll0_auxclk as the parent and new boards
  494. * should use device tree, so hard-coding the value (1) here.
  495. */
  496. parent = clk_hw_get_parent_by_index(&usb0->hw, 1);
  497. if (parent)
  498. clk_set_parent(usb0->hw.clk, parent->clk);
  499. else
  500. dev_warn(dev, "Failed to find usb0 parent clock\n");
  501. usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
  502. if (IS_ERR(usb1))
  503. return PTR_ERR(usb1);
  504. /*
  505. * All existing boards use usb0_clk48 as the parent and new boards
  506. * should use device tree, so hard-coding the value (0) here.
  507. */
  508. parent = clk_hw_get_parent_by_index(&usb1->hw, 0);
  509. if (parent)
  510. clk_set_parent(usb1->hw.clk, parent->clk);
  511. else
  512. dev_warn(dev, "Failed to find usb1 parent clock\n");
  513. clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy");
  514. clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy");
  515. return 0;
  516. }
  517. static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap)
  518. {
  519. struct clk_hw_onecell_data *clk_data;
  520. struct da8xx_usb0_clk48 *usb0;
  521. struct da8xx_usb1_clk48 *usb1;
  522. clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, 2),
  523. GFP_KERNEL);
  524. if (!clk_data)
  525. return -ENOMEM;
  526. clk_data->num = 2;
  527. usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
  528. if (IS_ERR(usb0)) {
  529. if (PTR_ERR(usb0) == -EPROBE_DEFER)
  530. return -EPROBE_DEFER;
  531. dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n",
  532. PTR_ERR(usb0));
  533. clk_data->hws[0] = ERR_PTR(-ENOENT);
  534. } else {
  535. clk_data->hws[0] = &usb0->hw;
  536. }
  537. usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
  538. if (IS_ERR(usb1)) {
  539. if (PTR_ERR(usb1) == -EPROBE_DEFER)
  540. return -EPROBE_DEFER;
  541. dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n",
  542. PTR_ERR(usb1));
  543. clk_data->hws[1] = ERR_PTR(-ENOENT);
  544. } else {
  545. clk_data->hws[1] = &usb1->hw;
  546. }
  547. return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
  548. }
  549. /* --- platform device --- */
  550. static const struct of_device_id da8xx_cfgchip_of_match[] = {
  551. {
  552. .compatible = "ti,da830-tbclksync",
  553. .data = of_da8xx_tbclksync_init,
  554. },
  555. {
  556. .compatible = "ti,da830-div4p5ena",
  557. .data = of_da8xx_div4p5ena_init,
  558. },
  559. {
  560. .compatible = "ti,da850-async1-clksrc",
  561. .data = of_da850_async1_init,
  562. },
  563. {
  564. .compatible = "ti,da850-async3-clksrc",
  565. .data = of_da850_async3_init,
  566. },
  567. {
  568. .compatible = "ti,da830-usb-phy-clocks",
  569. .data = of_da8xx_usb_phy_clk_init,
  570. },
  571. { }
  572. };
  573. static const struct platform_device_id da8xx_cfgchip_id_table[] = {
  574. {
  575. .name = "da830-tbclksync",
  576. .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk,
  577. },
  578. {
  579. .name = "da830-div4p5ena",
  580. .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5,
  581. },
  582. {
  583. .name = "da850-async1-clksrc",
  584. .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1,
  585. },
  586. {
  587. .name = "da850-async3-clksrc",
  588. .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
  589. },
  590. {
  591. .name = "da830-usb-phy-clks",
  592. .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk,
  593. },
  594. { }
  595. };
  596. typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap);
  597. static int da8xx_cfgchip_probe(struct platform_device *pdev)
  598. {
  599. struct device *dev = &pdev->dev;
  600. struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data;
  601. const struct of_device_id *of_id;
  602. da8xx_cfgchip_init clk_init = NULL;
  603. struct regmap *regmap = NULL;
  604. of_id = of_match_device(da8xx_cfgchip_of_match, dev);
  605. if (of_id) {
  606. struct device_node *parent;
  607. clk_init = of_id->data;
  608. parent = of_get_parent(dev->of_node);
  609. regmap = syscon_node_to_regmap(parent);
  610. of_node_put(parent);
  611. } else if (pdev->id_entry && pdata) {
  612. clk_init = (void *)pdev->id_entry->driver_data;
  613. regmap = pdata->cfgchip;
  614. }
  615. if (!clk_init) {
  616. dev_err(dev, "unable to find driver data\n");
  617. return -EINVAL;
  618. }
  619. if (IS_ERR_OR_NULL(regmap)) {
  620. dev_err(dev, "no regmap for CFGCHIP syscon\n");
  621. return regmap ? PTR_ERR(regmap) : -ENOENT;
  622. }
  623. return clk_init(dev, regmap);
  624. }
  625. static struct platform_driver da8xx_cfgchip_driver = {
  626. .probe = da8xx_cfgchip_probe,
  627. .driver = {
  628. .name = "da8xx-cfgchip-clk",
  629. .of_match_table = da8xx_cfgchip_of_match,
  630. },
  631. .id_table = da8xx_cfgchip_id_table,
  632. };
  633. static int __init da8xx_cfgchip_driver_init(void)
  634. {
  635. return platform_driver_register(&da8xx_cfgchip_driver);
  636. }
  637. /* has to be postcore_initcall because PSC devices depend on the async3 clock */
  638. postcore_initcall(da8xx_cfgchip_driver_init);