clk-xgene.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * clk-xgene.c - AppliedMicro X-Gene Clock Interface
  4. *
  5. * Copyright (c) 2013, Applied Micro Circuits Corporation
  6. * Author: Loc Ho <lho@apm.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/of_address.h>
  15. /* Register SCU_PCPPLL bit fields */
  16. #define N_DIV_RD(src) ((src) & 0x000001ff)
  17. #define SC_N_DIV_RD(src) ((src) & 0x0000007f)
  18. #define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8)
  19. /* Register SCU_SOCPLL bit fields */
  20. #define CLKR_RD(src) (((src) & 0x07000000)>>24)
  21. #define CLKOD_RD(src) (((src) & 0x00300000)>>20)
  22. #define REGSPEC_RESET_F1_MASK 0x00010000
  23. #define CLKF_RD(src) (((src) & 0x000001ff))
  24. #define XGENE_CLK_DRIVER_VER "0.1"
  25. static DEFINE_SPINLOCK(clk_lock);
  26. static inline u32 xgene_clk_read(void __iomem *csr)
  27. {
  28. return readl_relaxed(csr);
  29. }
  30. static inline void xgene_clk_write(u32 data, void __iomem *csr)
  31. {
  32. writel_relaxed(data, csr);
  33. }
  34. /* PLL Clock */
  35. enum xgene_pll_type {
  36. PLL_TYPE_PCP = 0,
  37. PLL_TYPE_SOC = 1,
  38. };
  39. struct xgene_clk_pll {
  40. struct clk_hw hw;
  41. void __iomem *reg;
  42. spinlock_t *lock;
  43. u32 pll_offset;
  44. enum xgene_pll_type type;
  45. int version;
  46. };
  47. #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
  48. static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
  49. {
  50. struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
  51. u32 data;
  52. data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
  53. pr_debug("%s pll %s\n", clk_hw_get_name(hw),
  54. data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
  55. return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
  56. }
  57. static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
  58. unsigned long parent_rate)
  59. {
  60. struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
  61. unsigned long fref;
  62. unsigned long fvco;
  63. u32 pll;
  64. u32 nref;
  65. u32 nout;
  66. u32 nfb;
  67. pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
  68. if (pllclk->version <= 1) {
  69. if (pllclk->type == PLL_TYPE_PCP) {
  70. /*
  71. * PLL VCO = Reference clock * NF
  72. * PCP PLL = PLL_VCO / 2
  73. */
  74. nout = 2;
  75. fvco = parent_rate * (N_DIV_RD(pll) + 4);
  76. } else {
  77. /*
  78. * Fref = Reference Clock / NREF;
  79. * Fvco = Fref * NFB;
  80. * Fout = Fvco / NOUT;
  81. */
  82. nref = CLKR_RD(pll) + 1;
  83. nout = CLKOD_RD(pll) + 1;
  84. nfb = CLKF_RD(pll);
  85. fref = parent_rate / nref;
  86. fvco = fref * nfb;
  87. }
  88. } else {
  89. /*
  90. * fvco = Reference clock * FBDIVC
  91. * PLL freq = fvco / NOUT
  92. */
  93. nout = SC_OUTDIV2(pll) ? 2 : 3;
  94. fvco = parent_rate * SC_N_DIV_RD(pll);
  95. }
  96. pr_debug("%s pll recalc rate %ld parent %ld version %d\n",
  97. clk_hw_get_name(hw), fvco / nout, parent_rate,
  98. pllclk->version);
  99. return fvco / nout;
  100. }
  101. static const struct clk_ops xgene_clk_pll_ops = {
  102. .is_enabled = xgene_clk_pll_is_enabled,
  103. .recalc_rate = xgene_clk_pll_recalc_rate,
  104. };
  105. static struct clk *xgene_register_clk_pll(struct device *dev,
  106. const char *name, const char *parent_name,
  107. unsigned long flags, void __iomem *reg, u32 pll_offset,
  108. u32 type, spinlock_t *lock, int version)
  109. {
  110. struct xgene_clk_pll *apmclk;
  111. struct clk *clk;
  112. struct clk_init_data init;
  113. /* allocate the APM clock structure */
  114. apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
  115. if (!apmclk)
  116. return ERR_PTR(-ENOMEM);
  117. init.name = name;
  118. init.ops = &xgene_clk_pll_ops;
  119. init.flags = flags;
  120. init.parent_names = parent_name ? &parent_name : NULL;
  121. init.num_parents = parent_name ? 1 : 0;
  122. apmclk->version = version;
  123. apmclk->reg = reg;
  124. apmclk->lock = lock;
  125. apmclk->pll_offset = pll_offset;
  126. apmclk->type = type;
  127. apmclk->hw.init = &init;
  128. /* Register the clock */
  129. clk = clk_register(dev, &apmclk->hw);
  130. if (IS_ERR(clk)) {
  131. pr_err("%s: could not register clk %s\n", __func__, name);
  132. kfree(apmclk);
  133. return NULL;
  134. }
  135. return clk;
  136. }
  137. static int xgene_pllclk_version(struct device_node *np)
  138. {
  139. if (of_device_is_compatible(np, "apm,xgene-socpll-clock"))
  140. return 1;
  141. if (of_device_is_compatible(np, "apm,xgene-pcppll-clock"))
  142. return 1;
  143. return 2;
  144. }
  145. static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
  146. {
  147. const char *clk_name = np->full_name;
  148. struct clk *clk;
  149. void __iomem *reg;
  150. int version = xgene_pllclk_version(np);
  151. reg = of_iomap(np, 0);
  152. if (!reg) {
  153. pr_err("Unable to map CSR register for %pOF\n", np);
  154. return;
  155. }
  156. of_property_read_string(np, "clock-output-names", &clk_name);
  157. clk = xgene_register_clk_pll(NULL,
  158. clk_name, of_clk_get_parent_name(np, 0),
  159. 0, reg, 0, pll_type, &clk_lock,
  160. version);
  161. if (!IS_ERR(clk)) {
  162. of_clk_add_provider(np, of_clk_src_simple_get, clk);
  163. clk_register_clkdev(clk, clk_name, NULL);
  164. pr_debug("Add %s clock PLL\n", clk_name);
  165. }
  166. }
  167. static void xgene_socpllclk_init(struct device_node *np)
  168. {
  169. xgene_pllclk_init(np, PLL_TYPE_SOC);
  170. }
  171. static void xgene_pcppllclk_init(struct device_node *np)
  172. {
  173. xgene_pllclk_init(np, PLL_TYPE_PCP);
  174. }
  175. /**
  176. * struct xgene_clk_pmd - PMD clock
  177. *
  178. * @hw: handle between common and hardware-specific interfaces
  179. * @reg: register containing the fractional scale multiplier (scaler)
  180. * @shift: shift to the unit bit field
  181. * @denom: 1/denominator unit
  182. * @lock: register lock
  183. * Flags:
  184. * XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read
  185. * from the register plus one. For example,
  186. * 0 for (0 + 1) / denom,
  187. * 1 for (1 + 1) / denom and etc.
  188. * If this flag is set, it is
  189. * 0 for (denom - 0) / denom,
  190. * 1 for (denom - 1) / denom and etc.
  191. *
  192. */
  193. struct xgene_clk_pmd {
  194. struct clk_hw hw;
  195. void __iomem *reg;
  196. u8 shift;
  197. u32 mask;
  198. u64 denom;
  199. u32 flags;
  200. spinlock_t *lock;
  201. };
  202. #define to_xgene_clk_pmd(_hw) container_of(_hw, struct xgene_clk_pmd, hw)
  203. #define XGENE_CLK_PMD_SCALE_INVERTED BIT(0)
  204. #define XGENE_CLK_PMD_SHIFT 8
  205. #define XGENE_CLK_PMD_WIDTH 3
  206. static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
  207. unsigned long parent_rate)
  208. {
  209. struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
  210. unsigned long flags = 0;
  211. u64 ret, scale;
  212. u32 val;
  213. if (fd->lock)
  214. spin_lock_irqsave(fd->lock, flags);
  215. else
  216. __acquire(fd->lock);
  217. val = readl(fd->reg);
  218. if (fd->lock)
  219. spin_unlock_irqrestore(fd->lock, flags);
  220. else
  221. __release(fd->lock);
  222. ret = (u64)parent_rate;
  223. scale = (val & fd->mask) >> fd->shift;
  224. if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED)
  225. scale = fd->denom - scale;
  226. else
  227. scale++;
  228. /* freq = parent_rate * scaler / denom */
  229. do_div(ret, fd->denom);
  230. ret *= scale;
  231. if (ret == 0)
  232. ret = (u64)parent_rate;
  233. return ret;
  234. }
  235. static long xgene_clk_pmd_round_rate(struct clk_hw *hw, unsigned long rate,
  236. unsigned long *parent_rate)
  237. {
  238. struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
  239. u64 ret, scale;
  240. if (!rate || rate >= *parent_rate)
  241. return *parent_rate;
  242. /* freq = parent_rate * scaler / denom */
  243. ret = rate * fd->denom;
  244. scale = DIV_ROUND_UP_ULL(ret, *parent_rate);
  245. ret = (u64)*parent_rate * scale;
  246. do_div(ret, fd->denom);
  247. return ret;
  248. }
  249. static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate,
  250. unsigned long parent_rate)
  251. {
  252. struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
  253. unsigned long flags = 0;
  254. u64 scale, ret;
  255. u32 val;
  256. /*
  257. * Compute the scaler:
  258. *
  259. * freq = parent_rate * scaler / denom, or
  260. * scaler = freq * denom / parent_rate
  261. */
  262. ret = rate * fd->denom;
  263. scale = DIV_ROUND_UP_ULL(ret, (u64)parent_rate);
  264. /* Check if inverted */
  265. if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED)
  266. scale = fd->denom - scale;
  267. else
  268. scale--;
  269. if (fd->lock)
  270. spin_lock_irqsave(fd->lock, flags);
  271. else
  272. __acquire(fd->lock);
  273. val = readl(fd->reg);
  274. val &= ~fd->mask;
  275. val |= (scale << fd->shift);
  276. writel(val, fd->reg);
  277. if (fd->lock)
  278. spin_unlock_irqrestore(fd->lock, flags);
  279. else
  280. __release(fd->lock);
  281. return 0;
  282. }
  283. static const struct clk_ops xgene_clk_pmd_ops = {
  284. .recalc_rate = xgene_clk_pmd_recalc_rate,
  285. .round_rate = xgene_clk_pmd_round_rate,
  286. .set_rate = xgene_clk_pmd_set_rate,
  287. };
  288. static struct clk *
  289. xgene_register_clk_pmd(struct device *dev,
  290. const char *name, const char *parent_name,
  291. unsigned long flags, void __iomem *reg, u8 shift,
  292. u8 width, u64 denom, u32 clk_flags, spinlock_t *lock)
  293. {
  294. struct xgene_clk_pmd *fd;
  295. struct clk_init_data init;
  296. struct clk *clk;
  297. fd = kzalloc(sizeof(*fd), GFP_KERNEL);
  298. if (!fd)
  299. return ERR_PTR(-ENOMEM);
  300. init.name = name;
  301. init.ops = &xgene_clk_pmd_ops;
  302. init.flags = flags;
  303. init.parent_names = parent_name ? &parent_name : NULL;
  304. init.num_parents = parent_name ? 1 : 0;
  305. fd->reg = reg;
  306. fd->shift = shift;
  307. fd->mask = (BIT(width) - 1) << shift;
  308. fd->denom = denom;
  309. fd->flags = clk_flags;
  310. fd->lock = lock;
  311. fd->hw.init = &init;
  312. clk = clk_register(dev, &fd->hw);
  313. if (IS_ERR(clk)) {
  314. pr_err("%s: could not register clk %s\n", __func__, name);
  315. kfree(fd);
  316. return NULL;
  317. }
  318. return clk;
  319. }
  320. static void xgene_pmdclk_init(struct device_node *np)
  321. {
  322. const char *clk_name = np->full_name;
  323. void __iomem *csr_reg;
  324. struct resource res;
  325. struct clk *clk;
  326. u64 denom;
  327. u32 flags = 0;
  328. int rc;
  329. /* Check if the entry is disabled */
  330. if (!of_device_is_available(np))
  331. return;
  332. /* Parse the DTS register for resource */
  333. rc = of_address_to_resource(np, 0, &res);
  334. if (rc != 0) {
  335. pr_err("no DTS register for %pOF\n", np);
  336. return;
  337. }
  338. csr_reg = of_iomap(np, 0);
  339. if (!csr_reg) {
  340. pr_err("Unable to map resource for %pOF\n", np);
  341. return;
  342. }
  343. of_property_read_string(np, "clock-output-names", &clk_name);
  344. denom = BIT(XGENE_CLK_PMD_WIDTH);
  345. flags |= XGENE_CLK_PMD_SCALE_INVERTED;
  346. clk = xgene_register_clk_pmd(NULL, clk_name,
  347. of_clk_get_parent_name(np, 0), 0,
  348. csr_reg, XGENE_CLK_PMD_SHIFT,
  349. XGENE_CLK_PMD_WIDTH, denom,
  350. flags, &clk_lock);
  351. if (!IS_ERR(clk)) {
  352. of_clk_add_provider(np, of_clk_src_simple_get, clk);
  353. clk_register_clkdev(clk, clk_name, NULL);
  354. pr_debug("Add %s clock\n", clk_name);
  355. } else {
  356. if (csr_reg)
  357. iounmap(csr_reg);
  358. }
  359. }
  360. /* IP Clock */
  361. struct xgene_dev_parameters {
  362. void __iomem *csr_reg; /* CSR for IP clock */
  363. u32 reg_clk_offset; /* Offset to clock enable CSR */
  364. u32 reg_clk_mask; /* Mask bit for clock enable */
  365. u32 reg_csr_offset; /* Offset to CSR reset */
  366. u32 reg_csr_mask; /* Mask bit for disable CSR reset */
  367. void __iomem *divider_reg; /* CSR for divider */
  368. u32 reg_divider_offset; /* Offset to divider register */
  369. u32 reg_divider_shift; /* Bit shift to divider field */
  370. u32 reg_divider_width; /* Width of the bit to divider field */
  371. };
  372. struct xgene_clk {
  373. struct clk_hw hw;
  374. spinlock_t *lock;
  375. struct xgene_dev_parameters param;
  376. };
  377. #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
  378. static int xgene_clk_enable(struct clk_hw *hw)
  379. {
  380. struct xgene_clk *pclk = to_xgene_clk(hw);
  381. unsigned long flags = 0;
  382. u32 data;
  383. if (pclk->lock)
  384. spin_lock_irqsave(pclk->lock, flags);
  385. if (pclk->param.csr_reg) {
  386. pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
  387. /* First enable the clock */
  388. data = xgene_clk_read(pclk->param.csr_reg +
  389. pclk->param.reg_clk_offset);
  390. data |= pclk->param.reg_clk_mask;
  391. xgene_clk_write(data, pclk->param.csr_reg +
  392. pclk->param.reg_clk_offset);
  393. pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",
  394. clk_hw_get_name(hw),
  395. pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
  396. data);
  397. /* Second enable the CSR */
  398. data = xgene_clk_read(pclk->param.csr_reg +
  399. pclk->param.reg_csr_offset);
  400. data &= ~pclk->param.reg_csr_mask;
  401. xgene_clk_write(data, pclk->param.csr_reg +
  402. pclk->param.reg_csr_offset);
  403. pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",
  404. clk_hw_get_name(hw),
  405. pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
  406. data);
  407. }
  408. if (pclk->lock)
  409. spin_unlock_irqrestore(pclk->lock, flags);
  410. return 0;
  411. }
  412. static void xgene_clk_disable(struct clk_hw *hw)
  413. {
  414. struct xgene_clk *pclk = to_xgene_clk(hw);
  415. unsigned long flags = 0;
  416. u32 data;
  417. if (pclk->lock)
  418. spin_lock_irqsave(pclk->lock, flags);
  419. if (pclk->param.csr_reg) {
  420. pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
  421. /* First put the CSR in reset */
  422. data = xgene_clk_read(pclk->param.csr_reg +
  423. pclk->param.reg_csr_offset);
  424. data |= pclk->param.reg_csr_mask;
  425. xgene_clk_write(data, pclk->param.csr_reg +
  426. pclk->param.reg_csr_offset);
  427. /* Second disable the clock */
  428. data = xgene_clk_read(pclk->param.csr_reg +
  429. pclk->param.reg_clk_offset);
  430. data &= ~pclk->param.reg_clk_mask;
  431. xgene_clk_write(data, pclk->param.csr_reg +
  432. pclk->param.reg_clk_offset);
  433. }
  434. if (pclk->lock)
  435. spin_unlock_irqrestore(pclk->lock, flags);
  436. }
  437. static int xgene_clk_is_enabled(struct clk_hw *hw)
  438. {
  439. struct xgene_clk *pclk = to_xgene_clk(hw);
  440. u32 data = 0;
  441. if (pclk->param.csr_reg) {
  442. pr_debug("%s clock checking\n", clk_hw_get_name(hw));
  443. data = xgene_clk_read(pclk->param.csr_reg +
  444. pclk->param.reg_clk_offset);
  445. pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
  446. data & pclk->param.reg_clk_mask ? "enabled" :
  447. "disabled");
  448. }
  449. if (!pclk->param.csr_reg)
  450. return 1;
  451. return data & pclk->param.reg_clk_mask ? 1 : 0;
  452. }
  453. static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
  454. unsigned long parent_rate)
  455. {
  456. struct xgene_clk *pclk = to_xgene_clk(hw);
  457. u32 data;
  458. if (pclk->param.divider_reg) {
  459. data = xgene_clk_read(pclk->param.divider_reg +
  460. pclk->param.reg_divider_offset);
  461. data >>= pclk->param.reg_divider_shift;
  462. data &= (1 << pclk->param.reg_divider_width) - 1;
  463. pr_debug("%s clock recalc rate %ld parent %ld\n",
  464. clk_hw_get_name(hw),
  465. parent_rate / data, parent_rate);
  466. return parent_rate / data;
  467. } else {
  468. pr_debug("%s clock recalc rate %ld parent %ld\n",
  469. clk_hw_get_name(hw), parent_rate, parent_rate);
  470. return parent_rate;
  471. }
  472. }
  473. static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  474. unsigned long parent_rate)
  475. {
  476. struct xgene_clk *pclk = to_xgene_clk(hw);
  477. unsigned long flags = 0;
  478. u32 data;
  479. u32 divider;
  480. u32 divider_save;
  481. if (pclk->lock)
  482. spin_lock_irqsave(pclk->lock, flags);
  483. if (pclk->param.divider_reg) {
  484. /* Let's compute the divider */
  485. if (rate > parent_rate)
  486. rate = parent_rate;
  487. divider_save = divider = parent_rate / rate; /* Rounded down */
  488. divider &= (1 << pclk->param.reg_divider_width) - 1;
  489. divider <<= pclk->param.reg_divider_shift;
  490. /* Set new divider */
  491. data = xgene_clk_read(pclk->param.divider_reg +
  492. pclk->param.reg_divider_offset);
  493. data &= ~(((1 << pclk->param.reg_divider_width) - 1)
  494. << pclk->param.reg_divider_shift);
  495. data |= divider;
  496. xgene_clk_write(data, pclk->param.divider_reg +
  497. pclk->param.reg_divider_offset);
  498. pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
  499. parent_rate / divider_save);
  500. } else {
  501. divider_save = 1;
  502. }
  503. if (pclk->lock)
  504. spin_unlock_irqrestore(pclk->lock, flags);
  505. return parent_rate / divider_save;
  506. }
  507. static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  508. unsigned long *prate)
  509. {
  510. struct xgene_clk *pclk = to_xgene_clk(hw);
  511. unsigned long parent_rate = *prate;
  512. u32 divider;
  513. if (pclk->param.divider_reg) {
  514. /* Let's compute the divider */
  515. if (rate > parent_rate)
  516. rate = parent_rate;
  517. divider = parent_rate / rate; /* Rounded down */
  518. } else {
  519. divider = 1;
  520. }
  521. return parent_rate / divider;
  522. }
  523. static const struct clk_ops xgene_clk_ops = {
  524. .enable = xgene_clk_enable,
  525. .disable = xgene_clk_disable,
  526. .is_enabled = xgene_clk_is_enabled,
  527. .recalc_rate = xgene_clk_recalc_rate,
  528. .set_rate = xgene_clk_set_rate,
  529. .round_rate = xgene_clk_round_rate,
  530. };
  531. static struct clk *xgene_register_clk(struct device *dev,
  532. const char *name, const char *parent_name,
  533. struct xgene_dev_parameters *parameters, spinlock_t *lock)
  534. {
  535. struct xgene_clk *apmclk;
  536. struct clk *clk;
  537. struct clk_init_data init;
  538. int rc;
  539. /* allocate the APM clock structure */
  540. apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
  541. if (!apmclk)
  542. return ERR_PTR(-ENOMEM);
  543. init.name = name;
  544. init.ops = &xgene_clk_ops;
  545. init.flags = 0;
  546. init.parent_names = parent_name ? &parent_name : NULL;
  547. init.num_parents = parent_name ? 1 : 0;
  548. apmclk->lock = lock;
  549. apmclk->hw.init = &init;
  550. apmclk->param = *parameters;
  551. /* Register the clock */
  552. clk = clk_register(dev, &apmclk->hw);
  553. if (IS_ERR(clk)) {
  554. pr_err("%s: could not register clk %s\n", __func__, name);
  555. kfree(apmclk);
  556. return clk;
  557. }
  558. /* Register the clock for lookup */
  559. rc = clk_register_clkdev(clk, name, NULL);
  560. if (rc != 0) {
  561. pr_err("%s: could not register lookup clk %s\n",
  562. __func__, name);
  563. }
  564. return clk;
  565. }
  566. static void __init xgene_devclk_init(struct device_node *np)
  567. {
  568. const char *clk_name = np->full_name;
  569. struct clk *clk;
  570. struct resource res;
  571. int rc;
  572. struct xgene_dev_parameters parameters;
  573. int i;
  574. /* Check if the entry is disabled */
  575. if (!of_device_is_available(np))
  576. return;
  577. /* Parse the DTS register for resource */
  578. parameters.csr_reg = NULL;
  579. parameters.divider_reg = NULL;
  580. for (i = 0; i < 2; i++) {
  581. void __iomem *map_res;
  582. rc = of_address_to_resource(np, i, &res);
  583. if (rc != 0) {
  584. if (i == 0) {
  585. pr_err("no DTS register for %pOF\n", np);
  586. return;
  587. }
  588. break;
  589. }
  590. map_res = of_iomap(np, i);
  591. if (!map_res) {
  592. pr_err("Unable to map resource %d for %pOF\n", i, np);
  593. goto err;
  594. }
  595. if (strcmp(res.name, "div-reg") == 0)
  596. parameters.divider_reg = map_res;
  597. else /* if (strcmp(res->name, "csr-reg") == 0) */
  598. parameters.csr_reg = map_res;
  599. }
  600. if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))
  601. parameters.reg_csr_offset = 0;
  602. if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))
  603. parameters.reg_csr_mask = 0xF;
  604. if (of_property_read_u32(np, "enable-offset",
  605. &parameters.reg_clk_offset))
  606. parameters.reg_clk_offset = 0x8;
  607. if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))
  608. parameters.reg_clk_mask = 0xF;
  609. if (of_property_read_u32(np, "divider-offset",
  610. &parameters.reg_divider_offset))
  611. parameters.reg_divider_offset = 0;
  612. if (of_property_read_u32(np, "divider-width",
  613. &parameters.reg_divider_width))
  614. parameters.reg_divider_width = 0;
  615. if (of_property_read_u32(np, "divider-shift",
  616. &parameters.reg_divider_shift))
  617. parameters.reg_divider_shift = 0;
  618. of_property_read_string(np, "clock-output-names", &clk_name);
  619. clk = xgene_register_clk(NULL, clk_name,
  620. of_clk_get_parent_name(np, 0), &parameters, &clk_lock);
  621. if (IS_ERR(clk))
  622. goto err;
  623. pr_debug("Add %s clock\n", clk_name);
  624. rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
  625. if (rc != 0)
  626. pr_err("%s: could register provider clk %pOF\n", __func__, np);
  627. return;
  628. err:
  629. if (parameters.csr_reg)
  630. iounmap(parameters.csr_reg);
  631. if (parameters.divider_reg)
  632. iounmap(parameters.divider_reg);
  633. }
  634. CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
  635. CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
  636. CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init);
  637. CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
  638. xgene_socpllclk_init);
  639. CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
  640. xgene_pcppllclk_init);
  641. CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);