clk-wm831x.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * WM831x clock control
  4. *
  5. * Copyright 2011-2 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/delay.h>
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/mfd/wm831x/core.h>
  15. struct wm831x_clk {
  16. struct wm831x *wm831x;
  17. struct clk_hw xtal_hw;
  18. struct clk_hw fll_hw;
  19. struct clk_hw clkout_hw;
  20. bool xtal_ena;
  21. };
  22. static int wm831x_xtal_is_prepared(struct clk_hw *hw)
  23. {
  24. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  25. xtal_hw);
  26. return clkdata->xtal_ena;
  27. }
  28. static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
  29. unsigned long parent_rate)
  30. {
  31. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  32. xtal_hw);
  33. if (clkdata->xtal_ena)
  34. return 32768;
  35. else
  36. return 0;
  37. }
  38. static const struct clk_ops wm831x_xtal_ops = {
  39. .is_prepared = wm831x_xtal_is_prepared,
  40. .recalc_rate = wm831x_xtal_recalc_rate,
  41. };
  42. static const struct clk_init_data wm831x_xtal_init = {
  43. .name = "xtal",
  44. .ops = &wm831x_xtal_ops,
  45. };
  46. static const unsigned long wm831x_fll_auto_rates[] = {
  47. 2048000,
  48. 11289600,
  49. 12000000,
  50. 12288000,
  51. 19200000,
  52. 22579600,
  53. 24000000,
  54. 24576000,
  55. };
  56. static int wm831x_fll_is_prepared(struct clk_hw *hw)
  57. {
  58. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  59. fll_hw);
  60. struct wm831x *wm831x = clkdata->wm831x;
  61. int ret;
  62. ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
  63. if (ret < 0) {
  64. dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
  65. ret);
  66. return true;
  67. }
  68. return (ret & WM831X_FLL_ENA) != 0;
  69. }
  70. static int wm831x_fll_prepare(struct clk_hw *hw)
  71. {
  72. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  73. fll_hw);
  74. struct wm831x *wm831x = clkdata->wm831x;
  75. int ret;
  76. ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
  77. WM831X_FLL_ENA, WM831X_FLL_ENA);
  78. if (ret != 0)
  79. dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
  80. /* wait 2-3 ms for new frequency taking effect */
  81. usleep_range(2000, 3000);
  82. return ret;
  83. }
  84. static void wm831x_fll_unprepare(struct clk_hw *hw)
  85. {
  86. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  87. fll_hw);
  88. struct wm831x *wm831x = clkdata->wm831x;
  89. int ret;
  90. ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
  91. if (ret != 0)
  92. dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
  93. }
  94. static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
  95. unsigned long parent_rate)
  96. {
  97. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  98. fll_hw);
  99. struct wm831x *wm831x = clkdata->wm831x;
  100. int ret;
  101. ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
  102. if (ret < 0) {
  103. dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
  104. ret);
  105. return 0;
  106. }
  107. if (ret & WM831X_FLL_AUTO)
  108. return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
  109. dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
  110. return 0;
  111. }
  112. static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
  113. unsigned long *unused)
  114. {
  115. int best = 0;
  116. int i;
  117. for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
  118. if (abs(wm831x_fll_auto_rates[i] - rate) <
  119. abs(wm831x_fll_auto_rates[best] - rate))
  120. best = i;
  121. return wm831x_fll_auto_rates[best];
  122. }
  123. static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
  124. unsigned long parent_rate)
  125. {
  126. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  127. fll_hw);
  128. struct wm831x *wm831x = clkdata->wm831x;
  129. int i;
  130. for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
  131. if (wm831x_fll_auto_rates[i] == rate)
  132. break;
  133. if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
  134. return -EINVAL;
  135. if (wm831x_fll_is_prepared(hw))
  136. return -EPERM;
  137. return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
  138. WM831X_FLL_AUTO_FREQ_MASK, i);
  139. }
  140. static const char *wm831x_fll_parents[] = {
  141. "xtal",
  142. "clkin",
  143. };
  144. static u8 wm831x_fll_get_parent(struct clk_hw *hw)
  145. {
  146. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  147. fll_hw);
  148. struct wm831x *wm831x = clkdata->wm831x;
  149. int ret;
  150. /* AUTO mode is always clocked from the crystal */
  151. ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
  152. if (ret < 0) {
  153. dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
  154. ret);
  155. return 0;
  156. }
  157. if (ret & WM831X_FLL_AUTO)
  158. return 0;
  159. ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
  160. if (ret < 0) {
  161. dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
  162. ret);
  163. return 0;
  164. }
  165. switch (ret & WM831X_FLL_CLK_SRC_MASK) {
  166. case 0:
  167. return 0;
  168. case 1:
  169. return 1;
  170. default:
  171. dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
  172. ret & WM831X_FLL_CLK_SRC_MASK);
  173. return 0;
  174. }
  175. }
  176. static const struct clk_ops wm831x_fll_ops = {
  177. .is_prepared = wm831x_fll_is_prepared,
  178. .prepare = wm831x_fll_prepare,
  179. .unprepare = wm831x_fll_unprepare,
  180. .round_rate = wm831x_fll_round_rate,
  181. .recalc_rate = wm831x_fll_recalc_rate,
  182. .set_rate = wm831x_fll_set_rate,
  183. .get_parent = wm831x_fll_get_parent,
  184. };
  185. static const struct clk_init_data wm831x_fll_init = {
  186. .name = "fll",
  187. .ops = &wm831x_fll_ops,
  188. .parent_names = wm831x_fll_parents,
  189. .num_parents = ARRAY_SIZE(wm831x_fll_parents),
  190. .flags = CLK_SET_RATE_GATE,
  191. };
  192. static int wm831x_clkout_is_prepared(struct clk_hw *hw)
  193. {
  194. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  195. clkout_hw);
  196. struct wm831x *wm831x = clkdata->wm831x;
  197. int ret;
  198. ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
  199. if (ret < 0) {
  200. dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
  201. ret);
  202. return false;
  203. }
  204. return (ret & WM831X_CLKOUT_ENA) != 0;
  205. }
  206. static int wm831x_clkout_prepare(struct clk_hw *hw)
  207. {
  208. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  209. clkout_hw);
  210. struct wm831x *wm831x = clkdata->wm831x;
  211. int ret;
  212. ret = wm831x_reg_unlock(wm831x);
  213. if (ret != 0) {
  214. dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
  215. return ret;
  216. }
  217. ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
  218. WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
  219. if (ret != 0)
  220. dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
  221. wm831x_reg_lock(wm831x);
  222. return ret;
  223. }
  224. static void wm831x_clkout_unprepare(struct clk_hw *hw)
  225. {
  226. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  227. clkout_hw);
  228. struct wm831x *wm831x = clkdata->wm831x;
  229. int ret;
  230. ret = wm831x_reg_unlock(wm831x);
  231. if (ret != 0) {
  232. dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
  233. return;
  234. }
  235. ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
  236. WM831X_CLKOUT_ENA, 0);
  237. if (ret != 0)
  238. dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
  239. wm831x_reg_lock(wm831x);
  240. }
  241. static const char *wm831x_clkout_parents[] = {
  242. "fll",
  243. "xtal",
  244. };
  245. static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
  246. {
  247. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  248. clkout_hw);
  249. struct wm831x *wm831x = clkdata->wm831x;
  250. int ret;
  251. ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
  252. if (ret < 0) {
  253. dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
  254. ret);
  255. return 0;
  256. }
  257. if (ret & WM831X_CLKOUT_SRC)
  258. return 1;
  259. else
  260. return 0;
  261. }
  262. static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
  263. {
  264. struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
  265. clkout_hw);
  266. struct wm831x *wm831x = clkdata->wm831x;
  267. return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
  268. WM831X_CLKOUT_SRC,
  269. parent << WM831X_CLKOUT_SRC_SHIFT);
  270. }
  271. static const struct clk_ops wm831x_clkout_ops = {
  272. .is_prepared = wm831x_clkout_is_prepared,
  273. .prepare = wm831x_clkout_prepare,
  274. .unprepare = wm831x_clkout_unprepare,
  275. .get_parent = wm831x_clkout_get_parent,
  276. .set_parent = wm831x_clkout_set_parent,
  277. };
  278. static const struct clk_init_data wm831x_clkout_init = {
  279. .name = "clkout",
  280. .ops = &wm831x_clkout_ops,
  281. .parent_names = wm831x_clkout_parents,
  282. .num_parents = ARRAY_SIZE(wm831x_clkout_parents),
  283. .flags = CLK_SET_RATE_PARENT,
  284. };
  285. static int wm831x_clk_probe(struct platform_device *pdev)
  286. {
  287. struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
  288. struct wm831x_clk *clkdata;
  289. int ret;
  290. clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
  291. if (!clkdata)
  292. return -ENOMEM;
  293. clkdata->wm831x = wm831x;
  294. /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
  295. ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
  296. if (ret < 0) {
  297. dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
  298. ret);
  299. return ret;
  300. }
  301. clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
  302. clkdata->xtal_hw.init = &wm831x_xtal_init;
  303. ret = devm_clk_hw_register(&pdev->dev, &clkdata->xtal_hw);
  304. if (ret)
  305. return ret;
  306. clkdata->fll_hw.init = &wm831x_fll_init;
  307. ret = devm_clk_hw_register(&pdev->dev, &clkdata->fll_hw);
  308. if (ret)
  309. return ret;
  310. clkdata->clkout_hw.init = &wm831x_clkout_init;
  311. ret = devm_clk_hw_register(&pdev->dev, &clkdata->clkout_hw);
  312. if (ret)
  313. return ret;
  314. platform_set_drvdata(pdev, clkdata);
  315. return 0;
  316. }
  317. static struct platform_driver wm831x_clk_driver = {
  318. .probe = wm831x_clk_probe,
  319. .driver = {
  320. .name = "wm831x-clk",
  321. },
  322. };
  323. module_platform_driver(wm831x_clk_driver);
  324. /* Module information */
  325. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  326. MODULE_DESCRIPTION("WM831x clock driver");
  327. MODULE_LICENSE("GPL");
  328. MODULE_ALIAS("platform:wm831x-clk");