clk-versaclock5.c 32 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for IDT Versaclock 5
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. /*
  8. * Possible optimizations:
  9. * - Use spread spectrum
  10. * - Use integer divider in FOD if applicable
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/delay.h>
  15. #include <linux/i2c.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/rational.h>
  22. #include <linux/regmap.h>
  23. #include <linux/slab.h>
  24. #include <dt-bindings/clk/versaclock.h>
  25. /* VersaClock5 registers */
  26. #define VC5_OTP_CONTROL 0x00
  27. /* Factory-reserved register block */
  28. #define VC5_RSVD_DEVICE_ID 0x01
  29. #define VC5_RSVD_ADC_GAIN_7_0 0x02
  30. #define VC5_RSVD_ADC_GAIN_15_8 0x03
  31. #define VC5_RSVD_ADC_OFFSET_7_0 0x04
  32. #define VC5_RSVD_ADC_OFFSET_15_8 0x05
  33. #define VC5_RSVD_TEMPY 0x06
  34. #define VC5_RSVD_OFFSET_TBIN 0x07
  35. #define VC5_RSVD_GAIN 0x08
  36. #define VC5_RSVD_TEST_NP 0x09
  37. #define VC5_RSVD_UNUSED 0x0a
  38. #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
  39. #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
  40. #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
  41. #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
  42. #define VC5_RSVD_CLK_AMP_123 0x0f
  43. /* Configuration register block */
  44. #define VC5_PRIM_SRC_SHDN 0x10
  45. #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
  46. #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
  47. #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
  48. #define VC5_PRIM_SRC_SHDN_SP BIT(1)
  49. #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
  50. #define VC5_VCO_BAND 0x11
  51. #define VC5_XTAL_X1_LOAD_CAP 0x12
  52. #define VC5_XTAL_X2_LOAD_CAP 0x13
  53. #define VC5_REF_DIVIDER 0x15
  54. #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
  55. #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
  56. #define VC5_VCO_CTRL_AND_PREDIV 0x16
  57. #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
  58. #define VC5_FEEDBACK_INT_DIV 0x17
  59. #define VC5_FEEDBACK_INT_DIV_BITS 0x18
  60. #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
  61. #define VC5_RC_CONTROL0 0x1e
  62. #define VC5_RC_CONTROL1 0x1f
  63. /* These registers are named "Unused Factory Reserved Registers" */
  64. #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
  65. #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
  66. /* Output divider control for divider 1,2,3,4 */
  67. #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
  68. #define VC5_OUT_DIV_CONTROL_RESET BIT(7)
  69. #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
  70. #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
  71. #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
  72. #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
  73. #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
  74. #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
  75. #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
  76. #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
  77. #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
  78. #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
  79. #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
  80. /* Clock control register for clock 1,2 */
  81. #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
  82. #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
  83. #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
  84. #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
  85. #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
  86. #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
  87. #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
  88. #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
  89. #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
  90. #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
  91. #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
  92. #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  93. #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  94. #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  95. #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  96. #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
  97. #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  98. #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  99. #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  100. #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  101. #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  102. #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
  103. #define VC5_CLK_OE_SHDN 0x68
  104. #define VC5_CLK_OS_SHDN 0x69
  105. #define VC5_GLOBAL_REGISTER 0x76
  106. #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
  107. /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
  108. #define VC5_PLL_VCO_MIN 2500000000UL
  109. #define VC5_PLL_VCO_MAX 3000000000UL
  110. /* VC5 Input mux settings */
  111. #define VC5_MUX_IN_XIN BIT(0)
  112. #define VC5_MUX_IN_CLKIN BIT(1)
  113. /* Maximum number of clk_out supported by this driver */
  114. #define VC5_MAX_CLK_OUT_NUM 5
  115. /* Maximum number of FODs supported by this driver */
  116. #define VC5_MAX_FOD_NUM 4
  117. /* flags to describe chip features */
  118. /* chip has built-in oscilator */
  119. #define VC5_HAS_INTERNAL_XTAL BIT(0)
  120. /* chip has PFD requency doubler */
  121. #define VC5_HAS_PFD_FREQ_DBL BIT(1)
  122. /* chip has bits to disable FOD sync */
  123. #define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
  124. /* Supported IDT VC5 models. */
  125. enum vc5_model {
  126. IDT_VC5_5P49V5923,
  127. IDT_VC5_5P49V5925,
  128. IDT_VC5_5P49V5933,
  129. IDT_VC5_5P49V5935,
  130. IDT_VC6_5P49V6901,
  131. IDT_VC6_5P49V6965,
  132. };
  133. /* Structure to describe features of a particular VC5 model */
  134. struct vc5_chip_info {
  135. const enum vc5_model model;
  136. const unsigned int clk_fod_cnt;
  137. const unsigned int clk_out_cnt;
  138. const u32 flags;
  139. };
  140. struct vc5_driver_data;
  141. struct vc5_hw_data {
  142. struct clk_hw hw;
  143. struct vc5_driver_data *vc5;
  144. u32 div_int;
  145. u32 div_frc;
  146. unsigned int num;
  147. };
  148. struct vc5_out_data {
  149. struct clk_hw hw;
  150. struct vc5_driver_data *vc5;
  151. unsigned int num;
  152. unsigned int clk_output_cfg0;
  153. unsigned int clk_output_cfg0_mask;
  154. };
  155. struct vc5_driver_data {
  156. struct i2c_client *client;
  157. struct regmap *regmap;
  158. const struct vc5_chip_info *chip_info;
  159. struct clk *pin_xin;
  160. struct clk *pin_clkin;
  161. unsigned char clk_mux_ins;
  162. struct clk_hw clk_mux;
  163. struct clk_hw clk_mul;
  164. struct clk_hw clk_pfd;
  165. struct vc5_hw_data clk_pll;
  166. struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
  167. struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
  168. };
  169. /*
  170. * VersaClock5 i2c regmap
  171. */
  172. static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
  173. {
  174. /* Factory reserved regs, make them read-only */
  175. if (reg <= 0xf)
  176. return false;
  177. /* Factory reserved regs, make them read-only */
  178. if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
  179. return false;
  180. return true;
  181. }
  182. static const struct regmap_config vc5_regmap_config = {
  183. .reg_bits = 8,
  184. .val_bits = 8,
  185. .cache_type = REGCACHE_RBTREE,
  186. .max_register = 0x76,
  187. .writeable_reg = vc5_regmap_is_writeable,
  188. };
  189. /*
  190. * VersaClock5 input multiplexer between XTAL and CLKIN divider
  191. */
  192. static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
  193. {
  194. struct vc5_driver_data *vc5 =
  195. container_of(hw, struct vc5_driver_data, clk_mux);
  196. const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
  197. unsigned int src;
  198. regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
  199. src &= mask;
  200. if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
  201. return 0;
  202. if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
  203. return 1;
  204. dev_warn(&vc5->client->dev,
  205. "Invalid clock input configuration (%02x)\n", src);
  206. return 0;
  207. }
  208. static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
  209. {
  210. struct vc5_driver_data *vc5 =
  211. container_of(hw, struct vc5_driver_data, clk_mux);
  212. const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
  213. u8 src;
  214. if ((index > 1) || !vc5->clk_mux_ins)
  215. return -EINVAL;
  216. if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
  217. if (index == 0)
  218. src = VC5_PRIM_SRC_SHDN_EN_XTAL;
  219. if (index == 1)
  220. src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
  221. } else {
  222. if (index != 0)
  223. return -EINVAL;
  224. if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
  225. src = VC5_PRIM_SRC_SHDN_EN_XTAL;
  226. else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
  227. src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
  228. else /* Invalid; should have been caught by vc5_probe() */
  229. return -EINVAL;
  230. }
  231. return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
  232. }
  233. static const struct clk_ops vc5_mux_ops = {
  234. .set_parent = vc5_mux_set_parent,
  235. .get_parent = vc5_mux_get_parent,
  236. };
  237. static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
  238. unsigned long parent_rate)
  239. {
  240. struct vc5_driver_data *vc5 =
  241. container_of(hw, struct vc5_driver_data, clk_mul);
  242. unsigned int premul;
  243. regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
  244. if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
  245. parent_rate *= 2;
  246. return parent_rate;
  247. }
  248. static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
  249. unsigned long *parent_rate)
  250. {
  251. if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
  252. return rate;
  253. else
  254. return -EINVAL;
  255. }
  256. static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
  257. unsigned long parent_rate)
  258. {
  259. struct vc5_driver_data *vc5 =
  260. container_of(hw, struct vc5_driver_data, clk_mul);
  261. u32 mask;
  262. if ((parent_rate * 2) == rate)
  263. mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
  264. else
  265. mask = 0;
  266. regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
  267. VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
  268. mask);
  269. return 0;
  270. }
  271. static const struct clk_ops vc5_dbl_ops = {
  272. .recalc_rate = vc5_dbl_recalc_rate,
  273. .round_rate = vc5_dbl_round_rate,
  274. .set_rate = vc5_dbl_set_rate,
  275. };
  276. static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
  277. unsigned long parent_rate)
  278. {
  279. struct vc5_driver_data *vc5 =
  280. container_of(hw, struct vc5_driver_data, clk_pfd);
  281. unsigned int prediv, div;
  282. regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
  283. /* The bypass_prediv is set, PLL fed from Ref_in directly. */
  284. if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
  285. return parent_rate;
  286. regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
  287. /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
  288. if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
  289. return parent_rate / 2;
  290. else
  291. return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
  292. }
  293. static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
  294. unsigned long *parent_rate)
  295. {
  296. unsigned long idiv;
  297. /* PLL cannot operate with input clock above 50 MHz. */
  298. if (rate > 50000000)
  299. return -EINVAL;
  300. /* CLKIN within range of PLL input, feed directly to PLL. */
  301. if (*parent_rate <= 50000000)
  302. return *parent_rate;
  303. idiv = DIV_ROUND_UP(*parent_rate, rate);
  304. if (idiv > 127)
  305. return -EINVAL;
  306. return *parent_rate / idiv;
  307. }
  308. static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
  309. unsigned long parent_rate)
  310. {
  311. struct vc5_driver_data *vc5 =
  312. container_of(hw, struct vc5_driver_data, clk_pfd);
  313. unsigned long idiv;
  314. u8 div;
  315. /* CLKIN within range of PLL input, feed directly to PLL. */
  316. if (parent_rate <= 50000000) {
  317. regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
  318. VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
  319. VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
  320. regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
  321. return 0;
  322. }
  323. idiv = DIV_ROUND_UP(parent_rate, rate);
  324. /* We have dedicated div-2 predivider. */
  325. if (idiv == 2)
  326. div = VC5_REF_DIVIDER_SEL_PREDIV2;
  327. else
  328. div = VC5_REF_DIVIDER_REF_DIV(idiv);
  329. regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
  330. regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
  331. VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
  332. return 0;
  333. }
  334. static const struct clk_ops vc5_pfd_ops = {
  335. .recalc_rate = vc5_pfd_recalc_rate,
  336. .round_rate = vc5_pfd_round_rate,
  337. .set_rate = vc5_pfd_set_rate,
  338. };
  339. /*
  340. * VersaClock5 PLL/VCO
  341. */
  342. static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
  343. unsigned long parent_rate)
  344. {
  345. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  346. struct vc5_driver_data *vc5 = hwdata->vc5;
  347. u32 div_int, div_frc;
  348. u8 fb[5];
  349. regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
  350. div_int = (fb[0] << 4) | (fb[1] >> 4);
  351. div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
  352. /* The PLL divider has 12 integer bits and 24 fractional bits */
  353. return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
  354. }
  355. static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  356. unsigned long *parent_rate)
  357. {
  358. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  359. u32 div_int;
  360. u64 div_frc;
  361. if (rate < VC5_PLL_VCO_MIN)
  362. rate = VC5_PLL_VCO_MIN;
  363. if (rate > VC5_PLL_VCO_MAX)
  364. rate = VC5_PLL_VCO_MAX;
  365. /* Determine integer part, which is 12 bit wide */
  366. div_int = rate / *parent_rate;
  367. if (div_int > 0xfff)
  368. rate = *parent_rate * 0xfff;
  369. /* Determine best fractional part, which is 24 bit wide */
  370. div_frc = rate % *parent_rate;
  371. div_frc *= BIT(24) - 1;
  372. do_div(div_frc, *parent_rate);
  373. hwdata->div_int = div_int;
  374. hwdata->div_frc = (u32)div_frc;
  375. return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
  376. }
  377. static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  378. unsigned long parent_rate)
  379. {
  380. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  381. struct vc5_driver_data *vc5 = hwdata->vc5;
  382. u8 fb[5];
  383. fb[0] = hwdata->div_int >> 4;
  384. fb[1] = hwdata->div_int << 4;
  385. fb[2] = hwdata->div_frc >> 16;
  386. fb[3] = hwdata->div_frc >> 8;
  387. fb[4] = hwdata->div_frc;
  388. return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
  389. }
  390. static const struct clk_ops vc5_pll_ops = {
  391. .recalc_rate = vc5_pll_recalc_rate,
  392. .round_rate = vc5_pll_round_rate,
  393. .set_rate = vc5_pll_set_rate,
  394. };
  395. static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
  396. unsigned long parent_rate)
  397. {
  398. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  399. struct vc5_driver_data *vc5 = hwdata->vc5;
  400. /* VCO frequency is divided by two before entering FOD */
  401. u32 f_in = parent_rate / 2;
  402. u32 div_int, div_frc;
  403. u8 od_int[2];
  404. u8 od_frc[4];
  405. regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
  406. od_int, 2);
  407. regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
  408. od_frc, 4);
  409. div_int = (od_int[0] << 4) | (od_int[1] >> 4);
  410. div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
  411. (od_frc[2] << 6) | (od_frc[3] >> 2);
  412. /* Avoid division by zero if the output is not configured. */
  413. if (div_int == 0 && div_frc == 0)
  414. return 0;
  415. /* The PLL divider has 12 integer bits and 30 fractional bits */
  416. return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
  417. }
  418. static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
  419. unsigned long *parent_rate)
  420. {
  421. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  422. /* VCO frequency is divided by two before entering FOD */
  423. u32 f_in = *parent_rate / 2;
  424. u32 div_int;
  425. u64 div_frc;
  426. /* Determine integer part, which is 12 bit wide */
  427. div_int = f_in / rate;
  428. /*
  429. * WARNING: The clock chip does not output signal if the integer part
  430. * of the divider is 0xfff and fractional part is non-zero.
  431. * Clamp the divider at 0xffe to keep the code simple.
  432. */
  433. if (div_int > 0xffe) {
  434. div_int = 0xffe;
  435. rate = f_in / div_int;
  436. }
  437. /* Determine best fractional part, which is 30 bit wide */
  438. div_frc = f_in % rate;
  439. div_frc <<= 24;
  440. do_div(div_frc, rate);
  441. hwdata->div_int = div_int;
  442. hwdata->div_frc = (u32)div_frc;
  443. return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
  444. }
  445. static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
  446. unsigned long parent_rate)
  447. {
  448. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  449. struct vc5_driver_data *vc5 = hwdata->vc5;
  450. u8 data[14] = {
  451. hwdata->div_frc >> 22, hwdata->div_frc >> 14,
  452. hwdata->div_frc >> 6, hwdata->div_frc << 2,
  453. 0, 0, 0, 0, 0,
  454. 0, 0,
  455. hwdata->div_int >> 4, hwdata->div_int << 4,
  456. 0
  457. };
  458. regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
  459. data, 14);
  460. /*
  461. * Toggle magic bit in undocumented register for unknown reason.
  462. * This is what the IDT timing commander tool does and the chip
  463. * datasheet somewhat implies this is needed, but the register
  464. * and the bit is not documented.
  465. */
  466. regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
  467. VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
  468. regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
  469. VC5_GLOBAL_REGISTER_GLOBAL_RESET,
  470. VC5_GLOBAL_REGISTER_GLOBAL_RESET);
  471. return 0;
  472. }
  473. static const struct clk_ops vc5_fod_ops = {
  474. .recalc_rate = vc5_fod_recalc_rate,
  475. .round_rate = vc5_fod_round_rate,
  476. .set_rate = vc5_fod_set_rate,
  477. };
  478. static int vc5_clk_out_prepare(struct clk_hw *hw)
  479. {
  480. struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
  481. struct vc5_driver_data *vc5 = hwdata->vc5;
  482. const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
  483. VC5_OUT_DIV_CONTROL_SEL_EXT |
  484. VC5_OUT_DIV_CONTROL_EN_FOD;
  485. unsigned int src;
  486. int ret;
  487. /*
  488. * When enabling a FOD, all currently enabled FODs are briefly
  489. * stopped in order to synchronize all of them. This causes a clock
  490. * disruption to any unrelated chips that might be already using
  491. * other clock outputs. Bypass the sync feature to avoid the issue,
  492. * which is possible on the VersaClock 6E family via reserved
  493. * registers.
  494. */
  495. if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
  496. ret = regmap_update_bits(vc5->regmap,
  497. VC5_RESERVED_X0(hwdata->num),
  498. VC5_RESERVED_X0_BYPASS_SYNC,
  499. VC5_RESERVED_X0_BYPASS_SYNC);
  500. if (ret)
  501. return ret;
  502. }
  503. /*
  504. * If the input mux is disabled, enable it first and
  505. * select source from matching FOD.
  506. */
  507. regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
  508. if ((src & mask) == 0) {
  509. src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
  510. ret = regmap_update_bits(vc5->regmap,
  511. VC5_OUT_DIV_CONTROL(hwdata->num),
  512. mask | VC5_OUT_DIV_CONTROL_RESET, src);
  513. if (ret)
  514. return ret;
  515. }
  516. /* Enable the clock buffer */
  517. regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
  518. VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
  519. VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
  520. if (hwdata->clk_output_cfg0_mask) {
  521. dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
  522. hwdata->num, hwdata->clk_output_cfg0_mask,
  523. hwdata->clk_output_cfg0);
  524. regmap_update_bits(vc5->regmap,
  525. VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
  526. hwdata->clk_output_cfg0_mask,
  527. hwdata->clk_output_cfg0);
  528. }
  529. return 0;
  530. }
  531. static void vc5_clk_out_unprepare(struct clk_hw *hw)
  532. {
  533. struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
  534. struct vc5_driver_data *vc5 = hwdata->vc5;
  535. /* Disable the clock buffer */
  536. regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
  537. VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
  538. }
  539. static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
  540. {
  541. struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
  542. struct vc5_driver_data *vc5 = hwdata->vc5;
  543. const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
  544. VC5_OUT_DIV_CONTROL_SEL_EXT |
  545. VC5_OUT_DIV_CONTROL_EN_FOD;
  546. const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
  547. VC5_OUT_DIV_CONTROL_EN_FOD;
  548. const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
  549. VC5_OUT_DIV_CONTROL_SEL_EXT;
  550. unsigned int src;
  551. regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
  552. src &= mask;
  553. if (src == 0) /* Input mux set to DISABLED */
  554. return 0;
  555. if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
  556. return 0;
  557. if (src == extclk)
  558. return 1;
  559. dev_warn(&vc5->client->dev,
  560. "Invalid clock output configuration (%02x)\n", src);
  561. return 0;
  562. }
  563. static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
  564. {
  565. struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
  566. struct vc5_driver_data *vc5 = hwdata->vc5;
  567. const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
  568. VC5_OUT_DIV_CONTROL_SELB_NORM |
  569. VC5_OUT_DIV_CONTROL_SEL_EXT |
  570. VC5_OUT_DIV_CONTROL_EN_FOD;
  571. const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
  572. VC5_OUT_DIV_CONTROL_SEL_EXT;
  573. u8 src = VC5_OUT_DIV_CONTROL_RESET;
  574. if (index == 0)
  575. src |= VC5_OUT_DIV_CONTROL_EN_FOD;
  576. else
  577. src |= extclk;
  578. return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
  579. mask, src);
  580. }
  581. static const struct clk_ops vc5_clk_out_ops = {
  582. .prepare = vc5_clk_out_prepare,
  583. .unprepare = vc5_clk_out_unprepare,
  584. .set_parent = vc5_clk_out_set_parent,
  585. .get_parent = vc5_clk_out_get_parent,
  586. };
  587. static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
  588. void *data)
  589. {
  590. struct vc5_driver_data *vc5 = data;
  591. unsigned int idx = clkspec->args[0];
  592. if (idx >= vc5->chip_info->clk_out_cnt)
  593. return ERR_PTR(-EINVAL);
  594. return &vc5->clk_out[idx].hw;
  595. }
  596. static int vc5_map_index_to_output(const enum vc5_model model,
  597. const unsigned int n)
  598. {
  599. switch (model) {
  600. case IDT_VC5_5P49V5933:
  601. return (n == 0) ? 0 : 3;
  602. case IDT_VC5_5P49V5923:
  603. case IDT_VC5_5P49V5925:
  604. case IDT_VC5_5P49V5935:
  605. case IDT_VC6_5P49V6901:
  606. case IDT_VC6_5P49V6965:
  607. default:
  608. return n;
  609. }
  610. }
  611. static int vc5_update_mode(struct device_node *np_output,
  612. struct vc5_out_data *clk_out)
  613. {
  614. u32 value;
  615. if (!of_property_read_u32(np_output, "idt,mode", &value)) {
  616. clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
  617. switch (value) {
  618. case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
  619. case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
  620. case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
  621. case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
  622. case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
  623. case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
  624. case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
  625. clk_out->clk_output_cfg0 |=
  626. value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
  627. break;
  628. default:
  629. return -EINVAL;
  630. }
  631. }
  632. return 0;
  633. }
  634. static int vc5_update_power(struct device_node *np_output,
  635. struct vc5_out_data *clk_out)
  636. {
  637. u32 value;
  638. if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
  639. &value)) {
  640. clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
  641. switch (value) {
  642. case 1800000:
  643. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
  644. break;
  645. case 2500000:
  646. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
  647. break;
  648. case 3300000:
  649. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
  650. break;
  651. default:
  652. return -EINVAL;
  653. }
  654. }
  655. return 0;
  656. }
  657. static int vc5_update_slew(struct device_node *np_output,
  658. struct vc5_out_data *clk_out)
  659. {
  660. u32 value;
  661. if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
  662. clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
  663. switch (value) {
  664. case 80:
  665. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
  666. break;
  667. case 85:
  668. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
  669. break;
  670. case 90:
  671. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
  672. break;
  673. case 100:
  674. clk_out->clk_output_cfg0 |=
  675. VC5_CLK_OUTPUT_CFG0_SLEW_100;
  676. break;
  677. default:
  678. return -EINVAL;
  679. }
  680. }
  681. return 0;
  682. }
  683. static int vc5_get_output_config(struct i2c_client *client,
  684. struct vc5_out_data *clk_out)
  685. {
  686. struct device_node *np_output;
  687. char *child_name;
  688. int ret = 0;
  689. child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
  690. if (!child_name)
  691. return -ENOMEM;
  692. np_output = of_get_child_by_name(client->dev.of_node, child_name);
  693. kfree(child_name);
  694. if (!np_output)
  695. return 0;
  696. ret = vc5_update_mode(np_output, clk_out);
  697. if (ret)
  698. goto output_error;
  699. ret = vc5_update_power(np_output, clk_out);
  700. if (ret)
  701. goto output_error;
  702. ret = vc5_update_slew(np_output, clk_out);
  703. output_error:
  704. if (ret) {
  705. dev_err(&client->dev,
  706. "Invalid clock output configuration OUT%d\n",
  707. clk_out->num + 1);
  708. }
  709. of_node_put(np_output);
  710. return ret;
  711. }
  712. static const struct of_device_id clk_vc5_of_match[];
  713. static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
  714. {
  715. struct vc5_driver_data *vc5;
  716. struct clk_init_data init;
  717. const char *parent_names[2];
  718. unsigned int n, idx = 0;
  719. int ret;
  720. vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
  721. if (!vc5)
  722. return -ENOMEM;
  723. i2c_set_clientdata(client, vc5);
  724. vc5->client = client;
  725. vc5->chip_info = of_device_get_match_data(&client->dev);
  726. vc5->pin_xin = devm_clk_get(&client->dev, "xin");
  727. if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
  728. return -EPROBE_DEFER;
  729. vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
  730. if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
  731. return -EPROBE_DEFER;
  732. vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
  733. if (IS_ERR(vc5->regmap)) {
  734. dev_err(&client->dev, "failed to allocate register map\n");
  735. return PTR_ERR(vc5->regmap);
  736. }
  737. /* Register clock input mux */
  738. memset(&init, 0, sizeof(init));
  739. if (!IS_ERR(vc5->pin_xin)) {
  740. vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
  741. parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
  742. } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
  743. vc5->pin_xin = clk_register_fixed_rate(&client->dev,
  744. "internal-xtal", NULL,
  745. 0, 25000000);
  746. if (IS_ERR(vc5->pin_xin))
  747. return PTR_ERR(vc5->pin_xin);
  748. vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
  749. parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
  750. }
  751. if (!IS_ERR(vc5->pin_clkin)) {
  752. vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
  753. parent_names[init.num_parents++] =
  754. __clk_get_name(vc5->pin_clkin);
  755. }
  756. if (!init.num_parents) {
  757. dev_err(&client->dev, "no input clock specified!\n");
  758. return -EINVAL;
  759. }
  760. init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
  761. init.ops = &vc5_mux_ops;
  762. init.flags = 0;
  763. init.parent_names = parent_names;
  764. vc5->clk_mux.init = &init;
  765. ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
  766. if (ret)
  767. goto err_clk_register;
  768. kfree(init.name); /* clock framework made a copy of the name */
  769. if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
  770. /* Register frequency doubler */
  771. memset(&init, 0, sizeof(init));
  772. init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
  773. client->dev.of_node);
  774. init.ops = &vc5_dbl_ops;
  775. init.flags = CLK_SET_RATE_PARENT;
  776. init.parent_names = parent_names;
  777. parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
  778. init.num_parents = 1;
  779. vc5->clk_mul.init = &init;
  780. ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
  781. if (ret)
  782. goto err_clk_register;
  783. kfree(init.name); /* clock framework made a copy of the name */
  784. }
  785. /* Register PFD */
  786. memset(&init, 0, sizeof(init));
  787. init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
  788. init.ops = &vc5_pfd_ops;
  789. init.flags = CLK_SET_RATE_PARENT;
  790. init.parent_names = parent_names;
  791. if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
  792. parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
  793. else
  794. parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
  795. init.num_parents = 1;
  796. vc5->clk_pfd.init = &init;
  797. ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
  798. if (ret)
  799. goto err_clk_register;
  800. kfree(init.name); /* clock framework made a copy of the name */
  801. /* Register PLL */
  802. memset(&init, 0, sizeof(init));
  803. init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
  804. init.ops = &vc5_pll_ops;
  805. init.flags = CLK_SET_RATE_PARENT;
  806. init.parent_names = parent_names;
  807. parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
  808. init.num_parents = 1;
  809. vc5->clk_pll.num = 0;
  810. vc5->clk_pll.vc5 = vc5;
  811. vc5->clk_pll.hw.init = &init;
  812. ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
  813. if (ret)
  814. goto err_clk_register;
  815. kfree(init.name); /* clock framework made a copy of the name */
  816. /* Register FODs */
  817. for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
  818. idx = vc5_map_index_to_output(vc5->chip_info->model, n);
  819. memset(&init, 0, sizeof(init));
  820. init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
  821. client->dev.of_node, idx);
  822. init.ops = &vc5_fod_ops;
  823. init.flags = CLK_SET_RATE_PARENT;
  824. init.parent_names = parent_names;
  825. parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
  826. init.num_parents = 1;
  827. vc5->clk_fod[n].num = idx;
  828. vc5->clk_fod[n].vc5 = vc5;
  829. vc5->clk_fod[n].hw.init = &init;
  830. ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
  831. if (ret)
  832. goto err_clk_register;
  833. kfree(init.name); /* clock framework made a copy of the name */
  834. }
  835. /* Register MUX-connected OUT0_I2C_SELB output */
  836. memset(&init, 0, sizeof(init));
  837. init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
  838. client->dev.of_node);
  839. init.ops = &vc5_clk_out_ops;
  840. init.flags = CLK_SET_RATE_PARENT;
  841. init.parent_names = parent_names;
  842. parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
  843. init.num_parents = 1;
  844. vc5->clk_out[0].num = idx;
  845. vc5->clk_out[0].vc5 = vc5;
  846. vc5->clk_out[0].hw.init = &init;
  847. ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
  848. if (ret)
  849. goto err_clk_register;
  850. kfree(init.name); /* clock framework made a copy of the name */
  851. /* Register FOD-connected OUTx outputs */
  852. for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
  853. idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
  854. parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
  855. if (n == 1)
  856. parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
  857. else
  858. parent_names[1] =
  859. clk_hw_get_name(&vc5->clk_out[n - 1].hw);
  860. memset(&init, 0, sizeof(init));
  861. init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
  862. client->dev.of_node, idx + 1);
  863. init.ops = &vc5_clk_out_ops;
  864. init.flags = CLK_SET_RATE_PARENT;
  865. init.parent_names = parent_names;
  866. init.num_parents = 2;
  867. vc5->clk_out[n].num = idx;
  868. vc5->clk_out[n].vc5 = vc5;
  869. vc5->clk_out[n].hw.init = &init;
  870. ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
  871. if (ret)
  872. goto err_clk_register;
  873. kfree(init.name); /* clock framework made a copy of the name */
  874. /* Fetch Clock Output configuration from DT (if specified) */
  875. ret = vc5_get_output_config(client, &vc5->clk_out[n]);
  876. if (ret)
  877. goto err_clk;
  878. }
  879. ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
  880. if (ret) {
  881. dev_err(&client->dev, "unable to add clk provider\n");
  882. goto err_clk;
  883. }
  884. return 0;
  885. err_clk_register:
  886. dev_err(&client->dev, "unable to register %s\n", init.name);
  887. kfree(init.name); /* clock framework made a copy of the name */
  888. err_clk:
  889. if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
  890. clk_unregister_fixed_rate(vc5->pin_xin);
  891. return ret;
  892. }
  893. static int vc5_remove(struct i2c_client *client)
  894. {
  895. struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
  896. of_clk_del_provider(client->dev.of_node);
  897. if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
  898. clk_unregister_fixed_rate(vc5->pin_xin);
  899. return 0;
  900. }
  901. static int __maybe_unused vc5_suspend(struct device *dev)
  902. {
  903. struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
  904. regcache_cache_only(vc5->regmap, true);
  905. regcache_mark_dirty(vc5->regmap);
  906. return 0;
  907. }
  908. static int __maybe_unused vc5_resume(struct device *dev)
  909. {
  910. struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
  911. int ret;
  912. regcache_cache_only(vc5->regmap, false);
  913. ret = regcache_sync(vc5->regmap);
  914. if (ret)
  915. dev_err(dev, "Failed to restore register map: %d\n", ret);
  916. return ret;
  917. }
  918. static const struct vc5_chip_info idt_5p49v5923_info = {
  919. .model = IDT_VC5_5P49V5923,
  920. .clk_fod_cnt = 2,
  921. .clk_out_cnt = 3,
  922. .flags = 0,
  923. };
  924. static const struct vc5_chip_info idt_5p49v5925_info = {
  925. .model = IDT_VC5_5P49V5925,
  926. .clk_fod_cnt = 4,
  927. .clk_out_cnt = 5,
  928. .flags = 0,
  929. };
  930. static const struct vc5_chip_info idt_5p49v5933_info = {
  931. .model = IDT_VC5_5P49V5933,
  932. .clk_fod_cnt = 2,
  933. .clk_out_cnt = 3,
  934. .flags = VC5_HAS_INTERNAL_XTAL,
  935. };
  936. static const struct vc5_chip_info idt_5p49v5935_info = {
  937. .model = IDT_VC5_5P49V5935,
  938. .clk_fod_cnt = 4,
  939. .clk_out_cnt = 5,
  940. .flags = VC5_HAS_INTERNAL_XTAL,
  941. };
  942. static const struct vc5_chip_info idt_5p49v6901_info = {
  943. .model = IDT_VC6_5P49V6901,
  944. .clk_fod_cnt = 4,
  945. .clk_out_cnt = 5,
  946. .flags = VC5_HAS_PFD_FREQ_DBL,
  947. };
  948. static const struct vc5_chip_info idt_5p49v6965_info = {
  949. .model = IDT_VC6_5P49V6965,
  950. .clk_fod_cnt = 4,
  951. .clk_out_cnt = 5,
  952. .flags = VC5_HAS_BYPASS_SYNC_BIT,
  953. };
  954. static const struct i2c_device_id vc5_id[] = {
  955. { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
  956. { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
  957. { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
  958. { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
  959. { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
  960. { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
  961. { }
  962. };
  963. MODULE_DEVICE_TABLE(i2c, vc5_id);
  964. static const struct of_device_id clk_vc5_of_match[] = {
  965. { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
  966. { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
  967. { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
  968. { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
  969. { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
  970. { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
  971. { },
  972. };
  973. MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
  974. static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
  975. static struct i2c_driver vc5_driver = {
  976. .driver = {
  977. .name = "vc5",
  978. .pm = &vc5_pm_ops,
  979. .of_match_table = clk_vc5_of_match,
  980. },
  981. .probe = vc5_probe,
  982. .remove = vc5_remove,
  983. .id_table = vc5_id,
  984. };
  985. module_i2c_driver(vc5_driver);
  986. MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
  987. MODULE_DESCRIPTION("IDT VersaClock 5 driver");
  988. MODULE_LICENSE("GPL");