clk-u300.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * U300 clock implementation
  4. * Copyright (C) 2007-2012 ST-Ericsson AB
  5. * Author: Linus Walleij <linus.walleij@stericsson.com>
  6. * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  7. */
  8. #include <linux/clkdev.h>
  9. #include <linux/slab.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_data/clk-u300.h>
  16. /* APP side SYSCON registers */
  17. /* CLK Control Register 16bit (R/W) */
  18. #define U300_SYSCON_CCR (0x0000)
  19. #define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
  20. #define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
  21. #define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
  22. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
  23. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
  24. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
  25. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
  26. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
  27. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
  28. /* CLK Status Register 16bit (R/W) */
  29. #define U300_SYSCON_CSR (0x0004)
  30. #define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
  31. #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
  32. /* Reset lines for SLOW devices 16bit (R/W) */
  33. #define U300_SYSCON_RSR (0x0014)
  34. #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
  35. #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
  36. #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
  37. #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
  38. #define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
  39. #define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
  40. #define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
  41. #define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
  42. #define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
  43. #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
  44. /* Reset lines for FAST devices 16bit (R/W) */
  45. #define U300_SYSCON_RFR (0x0018)
  46. #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
  47. #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
  48. #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
  49. #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
  50. #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
  51. #define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
  52. #define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
  53. #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
  54. /* Reset lines for the rest of the peripherals 16bit (R/W) */
  55. #define U300_SYSCON_RRR (0x001c)
  56. #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
  57. #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
  58. #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
  59. #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
  60. #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
  61. #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
  62. #define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
  63. #define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
  64. #define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
  65. #define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
  66. #define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
  67. #define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
  68. #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
  69. /* Clock enable for SLOW peripherals 16bit (R/W) */
  70. #define U300_SYSCON_CESR (0x0020)
  71. #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
  72. #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
  73. #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
  74. #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
  75. #define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
  76. #define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
  77. #define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
  78. #define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
  79. #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
  80. /* Clock enable for FAST peripherals 16bit (R/W) */
  81. #define U300_SYSCON_CEFR (0x0024)
  82. #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
  83. #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
  84. #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
  85. #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
  86. #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
  87. #define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
  88. #define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
  89. #define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
  90. #define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
  91. #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
  92. /* Clock enable for the rest of the peripherals 16bit (R/W) */
  93. #define U300_SYSCON_CERR (0x0028)
  94. #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
  95. #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
  96. #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
  97. #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
  98. #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
  99. #define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
  100. #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
  101. #define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
  102. #define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
  103. #define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
  104. #define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
  105. #define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
  106. #define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
  107. #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
  108. /* Single block clock enable 16bit (-/W) */
  109. #define U300_SYSCON_SBCER (0x002c)
  110. #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
  111. #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
  112. #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
  113. #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
  114. #define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
  115. #define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
  116. #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
  117. #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
  118. #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
  119. #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
  120. #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
  121. #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
  122. #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
  123. #define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
  124. #define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
  125. #define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
  126. #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
  127. #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
  128. #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
  129. #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
  130. #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
  131. #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
  132. #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
  133. #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
  134. #define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
  135. #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
  136. #define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
  137. #define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
  138. #define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
  139. #define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
  140. #define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
  141. #define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
  142. #define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
  143. /* Single block clock disable 16bit (-/W) */
  144. #define U300_SYSCON_SBCDR (0x0030)
  145. /* Same values as above for SBCER */
  146. /* Clock force SLOW peripherals 16bit (R/W) */
  147. #define U300_SYSCON_CFSR (0x003c)
  148. #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
  149. #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
  150. #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
  151. #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
  152. #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
  153. #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
  154. #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
  155. #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
  156. #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
  157. /* Clock force FAST peripherals 16bit (R/W) */
  158. #define U300_SYSCON_CFFR (0x40)
  159. /* Values not defined. Define if you want to use them. */
  160. /* Clock force the rest of the peripherals 16bit (R/W) */
  161. #define U300_SYSCON_CFRR (0x44)
  162. #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
  163. #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
  164. #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
  165. #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
  166. #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
  167. #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
  168. #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
  169. #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
  170. #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
  171. #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
  172. #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
  173. #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
  174. #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
  175. #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
  176. /* PLL208 Frequency Control 16bit (R/W) */
  177. #define U300_SYSCON_PFCR (0x48)
  178. #define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
  179. /* Power Management Control 16bit (R/W) */
  180. #define U300_SYSCON_PMCR (0x50)
  181. #define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
  182. #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
  183. /* Reset Out 16bit (R/W) */
  184. #define U300_SYSCON_RCR (0x6c)
  185. #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
  186. /* EMIF Slew Rate Control 16bit (R/W) */
  187. #define U300_SYSCON_SRCLR (0x70)
  188. #define U300_SYSCON_SRCLR_MASK (0x03FF)
  189. #define U300_SYSCON_SRCLR_VALUE (0x03FF)
  190. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
  191. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
  192. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
  193. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
  194. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
  195. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
  196. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
  197. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
  198. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
  199. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
  200. /* EMIF Clock Control Register 16bit (R/W) */
  201. #define U300_SYSCON_ECCR (0x0078)
  202. #define U300_SYSCON_ECCR_MASK (0x000F)
  203. #define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
  204. #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
  205. #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
  206. #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
  207. /* MMC/MSPRO frequency divider register 0 16bit (R/W) */
  208. #define U300_SYSCON_MMF0R (0x90)
  209. #define U300_SYSCON_MMF0R_MASK (0x00FF)
  210. #define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
  211. #define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
  212. /* MMC/MSPRO frequency divider register 1 16bit (R/W) */
  213. #define U300_SYSCON_MMF1R (0x94)
  214. #define U300_SYSCON_MMF1R_MASK (0x00FF)
  215. #define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
  216. #define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
  217. /* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
  218. #define U300_SYSCON_MMCR (0x9C)
  219. #define U300_SYSCON_MMCR_MASK (0x0003)
  220. #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
  221. #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
  222. /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
  223. #define U300_SYSCON_S0CCR (0x120)
  224. #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
  225. #define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
  226. #define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
  227. #define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
  228. #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
  229. #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
  230. #define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
  231. #define U300_SYSCON_S0CCR_SEL_MCLK (0x8 << 1)
  232. #define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA << 1)
  233. #define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC << 1)
  234. #define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD << 1)
  235. #define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE << 1)
  236. #define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0 << 1)
  237. #define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2 << 1)
  238. #define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4 << 1)
  239. #define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6 << 1)
  240. /* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
  241. #define U300_SYSCON_S1CCR (0x124)
  242. #define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
  243. #define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
  244. #define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
  245. #define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
  246. #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
  247. #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
  248. #define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
  249. #define U300_SYSCON_S1CCR_SEL_MCLK (0x8 << 1)
  250. #define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA << 1)
  251. #define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC << 1)
  252. #define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD << 1)
  253. #define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE << 1)
  254. #define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
  255. #define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2 << 1)
  256. #define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4 << 1)
  257. #define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6 << 1)
  258. /* SYS_2_CLK_CONTROL third clock control 16 bit (R/W) */
  259. #define U300_SYSCON_S2CCR (0x128)
  260. #define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
  261. #define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
  262. #define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
  263. #define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
  264. #define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
  265. #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
  266. #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
  267. #define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
  268. #define U300_SYSCON_S2CCR_SEL_MCLK (0x8 << 1)
  269. #define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA << 1)
  270. #define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC << 1)
  271. #define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD << 1)
  272. #define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE << 1)
  273. #define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
  274. #define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2 << 1)
  275. #define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4 << 1)
  276. #define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6 << 1)
  277. /* SC_PLL_IRQ_CONTROL 16bit (R/W) */
  278. #define U300_SYSCON_PICR (0x0130)
  279. #define U300_SYSCON_PICR_MASK (0x00FF)
  280. #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
  281. #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
  282. #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
  283. #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
  284. #define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
  285. #define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
  286. #define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
  287. #define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
  288. /* SC_PLL_IRQ_STATUS 16 bit (R/-) */
  289. #define U300_SYSCON_PISR (0x0134)
  290. #define U300_SYSCON_PISR_MASK (0x000F)
  291. #define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
  292. #define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
  293. #define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
  294. #define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
  295. /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
  296. #define U300_SYSCON_PICLR (0x0138)
  297. #define U300_SYSCON_PICLR_MASK (0x000F)
  298. #define U300_SYSCON_PICLR_RWMASK (0x0000)
  299. #define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
  300. #define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
  301. #define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
  302. #define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
  303. /* Clock activity observability register 0 */
  304. #define U300_SYSCON_C0OAR (0x140)
  305. #define U300_SYSCON_C0OAR_MASK (0xFFFF)
  306. #define U300_SYSCON_C0OAR_VALUE (0xFFFF)
  307. #define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
  308. #define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
  309. #define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
  310. #define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
  311. #define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
  312. #define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
  313. #define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
  314. #define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
  315. #define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
  316. #define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
  317. #define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
  318. #define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
  319. #define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
  320. #define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
  321. #define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
  322. #define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
  323. /* Clock activity observability register 1 */
  324. #define U300_SYSCON_C1OAR (0x144)
  325. #define U300_SYSCON_C1OAR_MASK (0x3FFE)
  326. #define U300_SYSCON_C1OAR_VALUE (0x3FFE)
  327. #define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
  328. #define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
  329. #define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
  330. #define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
  331. #define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
  332. #define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
  333. #define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
  334. #define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
  335. #define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
  336. #define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
  337. #define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
  338. #define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
  339. #define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
  340. /* Clock activity observability register 2 */
  341. #define U300_SYSCON_C2OAR (0x148)
  342. #define U300_SYSCON_C2OAR_MASK (0x0FFF)
  343. #define U300_SYSCON_C2OAR_VALUE (0x0FFF)
  344. #define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
  345. #define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
  346. #define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
  347. #define U300_SYSCON_C2OAR_VC_CLK (0x0100)
  348. #define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
  349. #define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
  350. #define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
  351. #define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
  352. #define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
  353. #define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
  354. #define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
  355. #define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
  356. /*
  357. * The clocking hierarchy currently looks like this.
  358. * NOTE: the idea is NOT to show how the clocks are routed on the chip!
  359. * The ideas is to show dependencies, so a clock higher up in the
  360. * hierarchy has to be on in order for another clock to be on. Now,
  361. * both CPU and DMA can actually be on top of the hierarchy, and that
  362. * is not modeled currently. Instead we have the backbone AMBA bus on
  363. * top. This bus cannot be programmed in any way but conceptually it
  364. * needs to be active for the bridges and devices to transport data.
  365. *
  366. * Please be aware that a few clocks are hw controlled, which mean that
  367. * the hw itself can turn on/off or change the rate of the clock when
  368. * needed!
  369. *
  370. * AMBA bus
  371. * |
  372. * +- CPU
  373. * +- FSMC NANDIF NAND Flash interface
  374. * +- SEMI Shared Memory interface
  375. * +- ISP Image Signal Processor (U335 only)
  376. * +- CDS (U335 only)
  377. * +- DMA Direct Memory Access Controller
  378. * +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL)
  379. * +- APEX
  380. * +- VIDEO_ENC AVE2/3 Video Encoder
  381. * +- XGAM Graphics Accelerator Controller
  382. * +- AHB
  383. * |
  384. * +- ahb:0 AHB Bridge
  385. * | |
  386. * | +- ahb:1 INTCON Interrupt controller
  387. * | +- ahb:3 MSPRO Memory Stick Pro controller
  388. * | +- ahb:4 EMIF External Memory interface
  389. * |
  390. * +- fast:0 FAST bridge
  391. * | |
  392. * | +- fast:1 MMCSD MMC/SD card reader controller
  393. * | +- fast:2 I2S0 PCM I2S channel 0 controller
  394. * | +- fast:3 I2S1 PCM I2S channel 1 controller
  395. * | +- fast:4 I2C0 I2C channel 0 controller
  396. * | +- fast:5 I2C1 I2C channel 1 controller
  397. * | +- fast:6 SPI SPI controller
  398. * | +- fast:7 UART1 Secondary UART (U335 only)
  399. * |
  400. * +- slow:0 SLOW bridge
  401. * |
  402. * +- slow:1 SYSCON (not possible to control)
  403. * +- slow:2 WDOG Watchdog
  404. * +- slow:3 UART0 primary UART
  405. * +- slow:4 TIMER_APP Application timer - used in Linux
  406. * +- slow:5 KEYPAD controller
  407. * +- slow:6 GPIO controller
  408. * +- slow:7 RTC controller
  409. * +- slow:8 BT Bus Tracer (not used currently)
  410. * +- slow:9 EH Event Handler (not used currently)
  411. * +- slow:a TIMER_ACC Access style timer (not used currently)
  412. * +- slow:b PPM (U335 only, what is that?)
  413. */
  414. /* Global syscon virtual base */
  415. static void __iomem *syscon_vbase;
  416. /**
  417. * struct clk_syscon - U300 syscon clock
  418. * @hw: corresponding clock hardware entry
  419. * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
  420. * and does not need any magic pokes to be enabled/disabled
  421. * @reset: state holder, whether this block's reset line is asserted or not
  422. * @res_reg: reset line enable/disable flag register
  423. * @res_bit: bit for resetting or taking this consumer out of reset
  424. * @en_reg: clock line enable/disable flag register
  425. * @en_bit: bit for enabling/disabling this consumer clock line
  426. * @clk_val: magic value to poke in the register to enable/disable
  427. * this one clock
  428. */
  429. struct clk_syscon {
  430. struct clk_hw hw;
  431. bool hw_ctrld;
  432. bool reset;
  433. void __iomem *res_reg;
  434. u8 res_bit;
  435. void __iomem *en_reg;
  436. u8 en_bit;
  437. u16 clk_val;
  438. };
  439. #define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
  440. static DEFINE_SPINLOCK(syscon_resetreg_lock);
  441. /*
  442. * Reset control functions. We remember if a block has been
  443. * taken out of reset and don't remove the reset assertion again
  444. * and vice versa. Currently we only remove resets so the
  445. * enablement function is defined out.
  446. */
  447. static void syscon_block_reset_enable(struct clk_syscon *sclk)
  448. {
  449. unsigned long iflags;
  450. u16 val;
  451. /* Not all blocks support resetting */
  452. if (!sclk->res_reg)
  453. return;
  454. spin_lock_irqsave(&syscon_resetreg_lock, iflags);
  455. val = readw(sclk->res_reg);
  456. val |= BIT(sclk->res_bit);
  457. writew(val, sclk->res_reg);
  458. spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
  459. sclk->reset = true;
  460. }
  461. static void syscon_block_reset_disable(struct clk_syscon *sclk)
  462. {
  463. unsigned long iflags;
  464. u16 val;
  465. /* Not all blocks support resetting */
  466. if (!sclk->res_reg)
  467. return;
  468. spin_lock_irqsave(&syscon_resetreg_lock, iflags);
  469. val = readw(sclk->res_reg);
  470. val &= ~BIT(sclk->res_bit);
  471. writew(val, sclk->res_reg);
  472. spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
  473. sclk->reset = false;
  474. }
  475. static int syscon_clk_prepare(struct clk_hw *hw)
  476. {
  477. struct clk_syscon *sclk = to_syscon(hw);
  478. /* If the block is in reset, bring it out */
  479. if (sclk->reset)
  480. syscon_block_reset_disable(sclk);
  481. return 0;
  482. }
  483. static void syscon_clk_unprepare(struct clk_hw *hw)
  484. {
  485. struct clk_syscon *sclk = to_syscon(hw);
  486. /* Please don't force the console into reset */
  487. if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
  488. return;
  489. /* When unpreparing, force block into reset */
  490. if (!sclk->reset)
  491. syscon_block_reset_enable(sclk);
  492. }
  493. static int syscon_clk_enable(struct clk_hw *hw)
  494. {
  495. struct clk_syscon *sclk = to_syscon(hw);
  496. /* Don't touch the hardware controlled clocks */
  497. if (sclk->hw_ctrld)
  498. return 0;
  499. /* These cannot be controlled */
  500. if (sclk->clk_val == 0xFFFFU)
  501. return 0;
  502. writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
  503. return 0;
  504. }
  505. static void syscon_clk_disable(struct clk_hw *hw)
  506. {
  507. struct clk_syscon *sclk = to_syscon(hw);
  508. /* Don't touch the hardware controlled clocks */
  509. if (sclk->hw_ctrld)
  510. return;
  511. if (sclk->clk_val == 0xFFFFU)
  512. return;
  513. /* Please don't disable the console port */
  514. if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
  515. return;
  516. writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
  517. }
  518. static int syscon_clk_is_enabled(struct clk_hw *hw)
  519. {
  520. struct clk_syscon *sclk = to_syscon(hw);
  521. u16 val;
  522. /* If no enable register defined, it's always-on */
  523. if (!sclk->en_reg)
  524. return 1;
  525. val = readw(sclk->en_reg);
  526. val &= BIT(sclk->en_bit);
  527. return val ? 1 : 0;
  528. }
  529. static u16 syscon_get_perf(void)
  530. {
  531. u16 val;
  532. val = readw(syscon_vbase + U300_SYSCON_CCR);
  533. val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
  534. return val;
  535. }
  536. static unsigned long
  537. syscon_clk_recalc_rate(struct clk_hw *hw,
  538. unsigned long parent_rate)
  539. {
  540. struct clk_syscon *sclk = to_syscon(hw);
  541. u16 perf = syscon_get_perf();
  542. switch (sclk->clk_val) {
  543. case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
  544. case U300_SYSCON_SBCER_I2C0_CLK_EN:
  545. case U300_SYSCON_SBCER_I2C1_CLK_EN:
  546. case U300_SYSCON_SBCER_MMC_CLK_EN:
  547. case U300_SYSCON_SBCER_SPI_CLK_EN:
  548. /* The FAST clocks have one progression */
  549. switch (perf) {
  550. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
  551. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
  552. return 13000000;
  553. default:
  554. return parent_rate; /* 26 MHz */
  555. }
  556. case U300_SYSCON_SBCER_DMAC_CLK_EN:
  557. case U300_SYSCON_SBCER_NANDIF_CLK_EN:
  558. case U300_SYSCON_SBCER_XGAM_CLK_EN:
  559. /* AMBA interconnect peripherals */
  560. switch (perf) {
  561. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
  562. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
  563. return 6500000;
  564. case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
  565. return 26000000;
  566. default:
  567. return parent_rate; /* 52 MHz */
  568. }
  569. case U300_SYSCON_SBCER_SEMI_CLK_EN:
  570. case U300_SYSCON_SBCER_EMIF_CLK_EN:
  571. /* EMIF speeds */
  572. switch (perf) {
  573. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
  574. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
  575. return 13000000;
  576. case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
  577. return 52000000;
  578. default:
  579. return 104000000;
  580. }
  581. case U300_SYSCON_SBCER_CPU_CLK_EN:
  582. /* And the fast CPU clock */
  583. switch (perf) {
  584. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
  585. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
  586. return 13000000;
  587. case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
  588. return 52000000;
  589. case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
  590. return 104000000;
  591. default:
  592. return parent_rate; /* 208 MHz */
  593. }
  594. default:
  595. /*
  596. * The SLOW clocks and default just inherit the rate of
  597. * their parent (typically PLL13 13 MHz).
  598. */
  599. return parent_rate;
  600. }
  601. }
  602. static long
  603. syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  604. unsigned long *prate)
  605. {
  606. struct clk_syscon *sclk = to_syscon(hw);
  607. if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
  608. return *prate;
  609. /* We really only support setting the rate of the CPU clock */
  610. if (rate <= 13000000)
  611. return 13000000;
  612. if (rate <= 52000000)
  613. return 52000000;
  614. if (rate <= 104000000)
  615. return 104000000;
  616. return 208000000;
  617. }
  618. static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  619. unsigned long parent_rate)
  620. {
  621. struct clk_syscon *sclk = to_syscon(hw);
  622. u16 val;
  623. /* We only support setting the rate of the CPU clock */
  624. if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
  625. return -EINVAL;
  626. switch (rate) {
  627. case 13000000:
  628. val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
  629. break;
  630. case 52000000:
  631. val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
  632. break;
  633. case 104000000:
  634. val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
  635. break;
  636. case 208000000:
  637. val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
  638. break;
  639. default:
  640. return -EINVAL;
  641. }
  642. val |= readw(syscon_vbase + U300_SYSCON_CCR) &
  643. ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
  644. writew(val, syscon_vbase + U300_SYSCON_CCR);
  645. return 0;
  646. }
  647. static const struct clk_ops syscon_clk_ops = {
  648. .prepare = syscon_clk_prepare,
  649. .unprepare = syscon_clk_unprepare,
  650. .enable = syscon_clk_enable,
  651. .disable = syscon_clk_disable,
  652. .is_enabled = syscon_clk_is_enabled,
  653. .recalc_rate = syscon_clk_recalc_rate,
  654. .round_rate = syscon_clk_round_rate,
  655. .set_rate = syscon_clk_set_rate,
  656. };
  657. static struct clk_hw * __init
  658. syscon_clk_register(struct device *dev, const char *name,
  659. const char *parent_name, unsigned long flags,
  660. bool hw_ctrld,
  661. void __iomem *res_reg, u8 res_bit,
  662. void __iomem *en_reg, u8 en_bit,
  663. u16 clk_val)
  664. {
  665. struct clk_hw *hw;
  666. struct clk_syscon *sclk;
  667. struct clk_init_data init;
  668. int ret;
  669. sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
  670. if (!sclk)
  671. return ERR_PTR(-ENOMEM);
  672. init.name = name;
  673. init.ops = &syscon_clk_ops;
  674. init.flags = flags;
  675. init.parent_names = (parent_name ? &parent_name : NULL);
  676. init.num_parents = (parent_name ? 1 : 0);
  677. sclk->hw.init = &init;
  678. sclk->hw_ctrld = hw_ctrld;
  679. /* Assume the block is in reset at registration */
  680. sclk->reset = true;
  681. sclk->res_reg = res_reg;
  682. sclk->res_bit = res_bit;
  683. sclk->en_reg = en_reg;
  684. sclk->en_bit = en_bit;
  685. sclk->clk_val = clk_val;
  686. hw = &sclk->hw;
  687. ret = clk_hw_register(dev, hw);
  688. if (ret) {
  689. kfree(sclk);
  690. hw = ERR_PTR(ret);
  691. }
  692. return hw;
  693. }
  694. #define U300_CLK_TYPE_SLOW 0
  695. #define U300_CLK_TYPE_FAST 1
  696. #define U300_CLK_TYPE_REST 2
  697. /**
  698. * struct u300_clock - defines the bits and pieces for a certain clock
  699. * @type: the clock type, slow fast or rest
  700. * @id: the bit in the slow/fast/rest register for this clock
  701. * @hw_ctrld: whether the clock is hardware controlled
  702. * @clk_val: a value to poke in the one-write enable/disable registers
  703. */
  704. struct u300_clock {
  705. u8 type;
  706. u8 id;
  707. bool hw_ctrld;
  708. u16 clk_val;
  709. };
  710. static struct u300_clock const u300_clk_lookup[] __initconst = {
  711. {
  712. .type = U300_CLK_TYPE_REST,
  713. .id = 3,
  714. .hw_ctrld = true,
  715. .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
  716. },
  717. {
  718. .type = U300_CLK_TYPE_REST,
  719. .id = 4,
  720. .hw_ctrld = true,
  721. .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
  722. },
  723. {
  724. .type = U300_CLK_TYPE_REST,
  725. .id = 5,
  726. .hw_ctrld = false,
  727. .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
  728. },
  729. {
  730. .type = U300_CLK_TYPE_REST,
  731. .id = 6,
  732. .hw_ctrld = false,
  733. .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
  734. },
  735. {
  736. .type = U300_CLK_TYPE_REST,
  737. .id = 8,
  738. .hw_ctrld = true,
  739. .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
  740. },
  741. {
  742. .type = U300_CLK_TYPE_REST,
  743. .id = 9,
  744. .hw_ctrld = false,
  745. .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
  746. },
  747. {
  748. .type = U300_CLK_TYPE_REST,
  749. .id = 10,
  750. .hw_ctrld = true,
  751. .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
  752. },
  753. {
  754. .type = U300_CLK_TYPE_REST,
  755. .id = 12,
  756. .hw_ctrld = false,
  757. /* INTCON: cannot be enabled, just taken out of reset */
  758. .clk_val = 0xFFFFU,
  759. },
  760. {
  761. .type = U300_CLK_TYPE_FAST,
  762. .id = 0,
  763. .hw_ctrld = true,
  764. .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
  765. },
  766. {
  767. .type = U300_CLK_TYPE_FAST,
  768. .id = 1,
  769. .hw_ctrld = false,
  770. .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
  771. },
  772. {
  773. .type = U300_CLK_TYPE_FAST,
  774. .id = 2,
  775. .hw_ctrld = false,
  776. .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
  777. },
  778. {
  779. .type = U300_CLK_TYPE_FAST,
  780. .id = 5,
  781. .hw_ctrld = false,
  782. .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
  783. },
  784. {
  785. .type = U300_CLK_TYPE_FAST,
  786. .id = 6,
  787. .hw_ctrld = false,
  788. .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
  789. },
  790. {
  791. .type = U300_CLK_TYPE_SLOW,
  792. .id = 0,
  793. .hw_ctrld = true,
  794. .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
  795. },
  796. {
  797. .type = U300_CLK_TYPE_SLOW,
  798. .id = 1,
  799. .hw_ctrld = false,
  800. .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
  801. },
  802. {
  803. .type = U300_CLK_TYPE_SLOW,
  804. .id = 4,
  805. .hw_ctrld = false,
  806. .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
  807. },
  808. {
  809. .type = U300_CLK_TYPE_SLOW,
  810. .id = 6,
  811. .hw_ctrld = true,
  812. /* No clock enable register bit */
  813. .clk_val = 0xFFFFU,
  814. },
  815. {
  816. .type = U300_CLK_TYPE_SLOW,
  817. .id = 7,
  818. .hw_ctrld = false,
  819. .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
  820. },
  821. {
  822. .type = U300_CLK_TYPE_SLOW,
  823. .id = 8,
  824. .hw_ctrld = false,
  825. .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
  826. },
  827. };
  828. static void __init of_u300_syscon_clk_init(struct device_node *np)
  829. {
  830. struct clk_hw *hw = ERR_PTR(-EINVAL);
  831. const char *clk_name = np->name;
  832. const char *parent_name;
  833. void __iomem *res_reg;
  834. void __iomem *en_reg;
  835. u32 clk_type;
  836. u32 clk_id;
  837. int i;
  838. if (of_property_read_u32(np, "clock-type", &clk_type)) {
  839. pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
  840. __func__, clk_name);
  841. return;
  842. }
  843. if (of_property_read_u32(np, "clock-id", &clk_id)) {
  844. pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
  845. __func__, clk_name);
  846. return;
  847. }
  848. parent_name = of_clk_get_parent_name(np, 0);
  849. switch (clk_type) {
  850. case U300_CLK_TYPE_SLOW:
  851. res_reg = syscon_vbase + U300_SYSCON_RSR;
  852. en_reg = syscon_vbase + U300_SYSCON_CESR;
  853. break;
  854. case U300_CLK_TYPE_FAST:
  855. res_reg = syscon_vbase + U300_SYSCON_RFR;
  856. en_reg = syscon_vbase + U300_SYSCON_CEFR;
  857. break;
  858. case U300_CLK_TYPE_REST:
  859. res_reg = syscon_vbase + U300_SYSCON_RRR;
  860. en_reg = syscon_vbase + U300_SYSCON_CERR;
  861. break;
  862. default:
  863. pr_err("unknown clock type %x specified\n", clk_type);
  864. return;
  865. }
  866. for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
  867. const struct u300_clock *u3clk = &u300_clk_lookup[i];
  868. if (u3clk->type == clk_type && u3clk->id == clk_id)
  869. hw = syscon_clk_register(NULL, clk_name, parent_name,
  870. 0, u3clk->hw_ctrld,
  871. res_reg, u3clk->id,
  872. en_reg, u3clk->id,
  873. u3clk->clk_val);
  874. }
  875. if (!IS_ERR(hw)) {
  876. of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
  877. /*
  878. * Some few system clocks - device tree does not
  879. * represent clocks without a corresponding device node.
  880. * for now we add these three clocks here.
  881. */
  882. if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
  883. clk_hw_register_clkdev(hw, NULL, "pl172");
  884. if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
  885. clk_hw_register_clkdev(hw, NULL, "semi");
  886. if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
  887. clk_hw_register_clkdev(hw, NULL, "intcon");
  888. }
  889. }
  890. /**
  891. * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
  892. * @hw: corresponding clock hardware entry
  893. * @is_mspro: if this is the memory stick clock rather than MMC/SD
  894. */
  895. struct clk_mclk {
  896. struct clk_hw hw;
  897. bool is_mspro;
  898. };
  899. #define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
  900. static int mclk_clk_prepare(struct clk_hw *hw)
  901. {
  902. struct clk_mclk *mclk = to_mclk(hw);
  903. u16 val;
  904. /* The MMC and MSPRO clocks need some special set-up */
  905. if (!mclk->is_mspro) {
  906. /* Set default MMC clock divisor to 18.9 MHz */
  907. writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
  908. val = readw(syscon_vbase + U300_SYSCON_MMCR);
  909. /* Disable the MMC feedback clock */
  910. val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
  911. /* Disable MSPRO frequency */
  912. val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
  913. writew(val, syscon_vbase + U300_SYSCON_MMCR);
  914. } else {
  915. val = readw(syscon_vbase + U300_SYSCON_MMCR);
  916. /* Disable the MMC feedback clock */
  917. val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
  918. /* Enable MSPRO frequency */
  919. val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
  920. writew(val, syscon_vbase + U300_SYSCON_MMCR);
  921. }
  922. return 0;
  923. }
  924. static unsigned long
  925. mclk_clk_recalc_rate(struct clk_hw *hw,
  926. unsigned long parent_rate)
  927. {
  928. u16 perf = syscon_get_perf();
  929. switch (perf) {
  930. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
  931. /*
  932. * Here, the 208 MHz PLL gets shut down and the always
  933. * on 13 MHz PLL used for RTC etc kicks into use
  934. * instead.
  935. */
  936. return 13000000;
  937. case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
  938. case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
  939. case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
  940. case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
  941. {
  942. /*
  943. * This clock is under program control. The register is
  944. * divided in two nybbles, bit 7-4 gives cycles-1 to count
  945. * high, bit 3-0 gives cycles-1 to count low. Distribute
  946. * these with no more than 1 cycle difference between
  947. * low and high and add low and high to get the actual
  948. * divisor. The base PLL is 208 MHz. Writing 0x00 will
  949. * divide by 1 and 1 so the highest frequency possible
  950. * is 104 MHz.
  951. *
  952. * e.g. 0x54 =>
  953. * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
  954. */
  955. u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
  956. U300_SYSCON_MMF0R_MASK;
  957. switch (val) {
  958. case 0x0054:
  959. return 18900000;
  960. case 0x0044:
  961. return 20800000;
  962. case 0x0043:
  963. return 23100000;
  964. case 0x0033:
  965. return 26000000;
  966. case 0x0032:
  967. return 29700000;
  968. case 0x0022:
  969. return 34700000;
  970. case 0x0021:
  971. return 41600000;
  972. case 0x0011:
  973. return 52000000;
  974. case 0x0000:
  975. return 104000000;
  976. default:
  977. break;
  978. }
  979. }
  980. default:
  981. break;
  982. }
  983. return parent_rate;
  984. }
  985. static long
  986. mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  987. unsigned long *prate)
  988. {
  989. if (rate <= 18900000)
  990. return 18900000;
  991. if (rate <= 20800000)
  992. return 20800000;
  993. if (rate <= 23100000)
  994. return 23100000;
  995. if (rate <= 26000000)
  996. return 26000000;
  997. if (rate <= 29700000)
  998. return 29700000;
  999. if (rate <= 34700000)
  1000. return 34700000;
  1001. if (rate <= 41600000)
  1002. return 41600000;
  1003. /* Highest rate */
  1004. return 52000000;
  1005. }
  1006. static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  1007. unsigned long parent_rate)
  1008. {
  1009. u16 val;
  1010. u16 reg;
  1011. switch (rate) {
  1012. case 18900000:
  1013. val = 0x0054;
  1014. break;
  1015. case 20800000:
  1016. val = 0x0044;
  1017. break;
  1018. case 23100000:
  1019. val = 0x0043;
  1020. break;
  1021. case 26000000:
  1022. val = 0x0033;
  1023. break;
  1024. case 29700000:
  1025. val = 0x0032;
  1026. break;
  1027. case 34700000:
  1028. val = 0x0022;
  1029. break;
  1030. case 41600000:
  1031. val = 0x0021;
  1032. break;
  1033. case 52000000:
  1034. val = 0x0011;
  1035. break;
  1036. case 104000000:
  1037. val = 0x0000;
  1038. break;
  1039. default:
  1040. return -EINVAL;
  1041. }
  1042. reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
  1043. ~U300_SYSCON_MMF0R_MASK;
  1044. writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
  1045. return 0;
  1046. }
  1047. static const struct clk_ops mclk_ops = {
  1048. .prepare = mclk_clk_prepare,
  1049. .recalc_rate = mclk_clk_recalc_rate,
  1050. .round_rate = mclk_clk_round_rate,
  1051. .set_rate = mclk_clk_set_rate,
  1052. };
  1053. static struct clk_hw * __init
  1054. mclk_clk_register(struct device *dev, const char *name,
  1055. const char *parent_name, bool is_mspro)
  1056. {
  1057. struct clk_hw *hw;
  1058. struct clk_mclk *mclk;
  1059. struct clk_init_data init;
  1060. int ret;
  1061. mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
  1062. if (!mclk)
  1063. return ERR_PTR(-ENOMEM);
  1064. init.name = "mclk";
  1065. init.ops = &mclk_ops;
  1066. init.flags = 0;
  1067. init.parent_names = (parent_name ? &parent_name : NULL);
  1068. init.num_parents = (parent_name ? 1 : 0);
  1069. mclk->hw.init = &init;
  1070. mclk->is_mspro = is_mspro;
  1071. hw = &mclk->hw;
  1072. ret = clk_hw_register(dev, hw);
  1073. if (ret) {
  1074. kfree(mclk);
  1075. hw = ERR_PTR(ret);
  1076. }
  1077. return hw;
  1078. }
  1079. static void __init of_u300_syscon_mclk_init(struct device_node *np)
  1080. {
  1081. struct clk_hw *hw;
  1082. const char *clk_name = np->name;
  1083. const char *parent_name;
  1084. parent_name = of_clk_get_parent_name(np, 0);
  1085. hw = mclk_clk_register(NULL, clk_name, parent_name, false);
  1086. if (!IS_ERR(hw))
  1087. of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
  1088. }
  1089. static const struct of_device_id u300_clk_match[] __initconst = {
  1090. {
  1091. .compatible = "fixed-clock",
  1092. .data = of_fixed_clk_setup,
  1093. },
  1094. {
  1095. .compatible = "fixed-factor-clock",
  1096. .data = of_fixed_factor_clk_setup,
  1097. },
  1098. {
  1099. .compatible = "stericsson,u300-syscon-clk",
  1100. .data = of_u300_syscon_clk_init,
  1101. },
  1102. {
  1103. .compatible = "stericsson,u300-syscon-mclk",
  1104. .data = of_u300_syscon_mclk_init,
  1105. },
  1106. {}
  1107. };
  1108. void __init u300_clk_init(void __iomem *base)
  1109. {
  1110. u16 val;
  1111. syscon_vbase = base;
  1112. /* Set system to run at PLL208, max performance, a known state. */
  1113. val = readw(syscon_vbase + U300_SYSCON_CCR);
  1114. val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
  1115. writew(val, syscon_vbase + U300_SYSCON_CCR);
  1116. /* Wait for the PLL208 to lock if not locked in yet */
  1117. while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
  1118. U300_SYSCON_CSR_PLL208_LOCK_IND));
  1119. /* Power management enable */
  1120. val = readw(syscon_vbase + U300_SYSCON_PMCR);
  1121. val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
  1122. writew(val, syscon_vbase + U300_SYSCON_PMCR);
  1123. of_clk_init(u300_clk_match);
  1124. }