clk-si544.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Silicon Labs Si544 Programmable Oscillator
  4. * Copyright (C) 2018 Topic Embedded Products
  5. * Author: Mike Looijmans <mike.looijmans@topic.nl>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/delay.h>
  9. #include <linux/math64.h>
  10. #include <linux/module.h>
  11. #include <linux/i2c.h>
  12. #include <linux/regmap.h>
  13. #include <linux/slab.h>
  14. /* I2C registers (decimal as in datasheet) */
  15. #define SI544_REG_CONTROL 7
  16. #define SI544_REG_OE_STATE 17
  17. #define SI544_REG_HS_DIV 23
  18. #define SI544_REG_LS_HS_DIV 24
  19. #define SI544_REG_FBDIV0 26
  20. #define SI544_REG_FBDIV8 27
  21. #define SI544_REG_FBDIV16 28
  22. #define SI544_REG_FBDIV24 29
  23. #define SI544_REG_FBDIV32 30
  24. #define SI544_REG_FBDIV40 31
  25. #define SI544_REG_FCAL_OVR 69
  26. #define SI544_REG_ADPLL_DELTA_M0 231
  27. #define SI544_REG_ADPLL_DELTA_M8 232
  28. #define SI544_REG_ADPLL_DELTA_M16 233
  29. #define SI544_REG_PAGE_SELECT 255
  30. /* Register values */
  31. #define SI544_CONTROL_RESET BIT(7)
  32. #define SI544_CONTROL_MS_ICAL2 BIT(3)
  33. #define SI544_OE_STATE_ODC_OE BIT(0)
  34. /* Max freq depends on speed grade */
  35. #define SI544_MIN_FREQ 200000U
  36. /* Si544 Internal oscilator runs at 55.05 MHz */
  37. #define FXO 55050000U
  38. /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
  39. #define FVCO_MIN 10800000000ULL
  40. #define HS_DIV_MAX 2046
  41. #define HS_DIV_MAX_ODD 33
  42. /* Lowest frequency synthesizeable using only the HS divider */
  43. #define MIN_HSDIV_FREQ (FVCO_MIN / HS_DIV_MAX)
  44. /* Range and interpretation of the adjustment value */
  45. #define DELTA_M_MAX 8161512
  46. #define DELTA_M_FRAC_NUM 19
  47. #define DELTA_M_FRAC_DEN 20000
  48. enum si544_speed_grade {
  49. si544a,
  50. si544b,
  51. si544c,
  52. };
  53. struct clk_si544 {
  54. struct clk_hw hw;
  55. struct regmap *regmap;
  56. struct i2c_client *i2c_client;
  57. enum si544_speed_grade speed_grade;
  58. };
  59. #define to_clk_si544(_hw) container_of(_hw, struct clk_si544, hw)
  60. /**
  61. * struct clk_si544_muldiv - Multiplier/divider settings
  62. * @fb_div_frac: integer part of feedback divider (32 bits)
  63. * @fb_div_int: fractional part of feedback divider (11 bits)
  64. * @hs_div: 1st divider, 5..2046, must be even when >33
  65. * @ls_div_bits: 2nd divider, as 2^x, range 0..5
  66. * If ls_div_bits is non-zero, hs_div must be even
  67. * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
  68. */
  69. struct clk_si544_muldiv {
  70. u32 fb_div_frac;
  71. u16 fb_div_int;
  72. u16 hs_div;
  73. u8 ls_div_bits;
  74. s32 delta_m;
  75. };
  76. /* Enables or disables the output driver */
  77. static int si544_enable_output(struct clk_si544 *data, bool enable)
  78. {
  79. return regmap_update_bits(data->regmap, SI544_REG_OE_STATE,
  80. SI544_OE_STATE_ODC_OE, enable ? SI544_OE_STATE_ODC_OE : 0);
  81. }
  82. static int si544_prepare(struct clk_hw *hw)
  83. {
  84. struct clk_si544 *data = to_clk_si544(hw);
  85. return si544_enable_output(data, true);
  86. }
  87. static void si544_unprepare(struct clk_hw *hw)
  88. {
  89. struct clk_si544 *data = to_clk_si544(hw);
  90. si544_enable_output(data, false);
  91. }
  92. static int si544_is_prepared(struct clk_hw *hw)
  93. {
  94. struct clk_si544 *data = to_clk_si544(hw);
  95. unsigned int val;
  96. int err;
  97. err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val);
  98. if (err < 0)
  99. return err;
  100. return !!(val & SI544_OE_STATE_ODC_OE);
  101. }
  102. /* Retrieve clock multiplier and dividers from hardware */
  103. static int si544_get_muldiv(struct clk_si544 *data,
  104. struct clk_si544_muldiv *settings)
  105. {
  106. int err;
  107. u8 reg[6];
  108. err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2);
  109. if (err)
  110. return err;
  111. settings->ls_div_bits = (reg[1] >> 4) & 0x07;
  112. settings->hs_div = (reg[1] & 0x07) << 8 | reg[0];
  113. err = regmap_bulk_read(data->regmap, SI544_REG_FBDIV0, reg, 6);
  114. if (err)
  115. return err;
  116. settings->fb_div_int = reg[4] | (reg[5] & 0x07) << 8;
  117. settings->fb_div_frac = reg[0] | reg[1] << 8 | reg[2] << 16 |
  118. reg[3] << 24;
  119. err = regmap_bulk_read(data->regmap, SI544_REG_ADPLL_DELTA_M0, reg, 3);
  120. if (err)
  121. return err;
  122. /* Interpret as 24-bit signed number */
  123. settings->delta_m = reg[0] << 8 | reg[1] << 16 | reg[2] << 24;
  124. settings->delta_m >>= 8;
  125. return 0;
  126. }
  127. static int si544_set_delta_m(struct clk_si544 *data, s32 delta_m)
  128. {
  129. u8 reg[3];
  130. reg[0] = delta_m;
  131. reg[1] = delta_m >> 8;
  132. reg[2] = delta_m >> 16;
  133. return regmap_bulk_write(data->regmap, SI544_REG_ADPLL_DELTA_M0,
  134. reg, 3);
  135. }
  136. static int si544_set_muldiv(struct clk_si544 *data,
  137. struct clk_si544_muldiv *settings)
  138. {
  139. int err;
  140. u8 reg[6];
  141. reg[0] = settings->hs_div;
  142. reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4;
  143. err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2);
  144. if (err < 0)
  145. return err;
  146. reg[0] = settings->fb_div_frac;
  147. reg[1] = settings->fb_div_frac >> 8;
  148. reg[2] = settings->fb_div_frac >> 16;
  149. reg[3] = settings->fb_div_frac >> 24;
  150. reg[4] = settings->fb_div_int;
  151. reg[5] = settings->fb_div_int >> 8;
  152. /*
  153. * Writing to SI544_REG_FBDIV40 triggers the clock change, so that
  154. * must be written last
  155. */
  156. return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6);
  157. }
  158. static bool is_valid_frequency(const struct clk_si544 *data,
  159. unsigned long frequency)
  160. {
  161. unsigned long max_freq = 0;
  162. if (frequency < SI544_MIN_FREQ)
  163. return false;
  164. switch (data->speed_grade) {
  165. case si544a:
  166. max_freq = 1500000000;
  167. break;
  168. case si544b:
  169. max_freq = 800000000;
  170. break;
  171. case si544c:
  172. max_freq = 350000000;
  173. break;
  174. }
  175. return frequency <= max_freq;
  176. }
  177. /* Calculate divider settings for a given frequency */
  178. static int si544_calc_muldiv(struct clk_si544_muldiv *settings,
  179. unsigned long frequency)
  180. {
  181. u64 vco;
  182. u32 ls_freq;
  183. u32 tmp;
  184. u8 res;
  185. /* Determine the minimum value of LS_DIV and resulting target freq. */
  186. ls_freq = frequency;
  187. settings->ls_div_bits = 0;
  188. if (frequency >= MIN_HSDIV_FREQ) {
  189. settings->ls_div_bits = 0;
  190. } else {
  191. res = 1;
  192. tmp = 2 * HS_DIV_MAX;
  193. while (tmp <= (HS_DIV_MAX * 32)) {
  194. if (((u64)frequency * tmp) >= FVCO_MIN)
  195. break;
  196. ++res;
  197. tmp <<= 1;
  198. }
  199. settings->ls_div_bits = res;
  200. ls_freq = frequency << res;
  201. }
  202. /* Determine minimum HS_DIV by rounding up */
  203. vco = FVCO_MIN + ls_freq - 1;
  204. do_div(vco, ls_freq);
  205. settings->hs_div = vco;
  206. /* round up to even number when required */
  207. if ((settings->hs_div & 1) &&
  208. (settings->hs_div > HS_DIV_MAX_ODD || settings->ls_div_bits))
  209. ++settings->hs_div;
  210. /* Calculate VCO frequency (in 10..12GHz range) */
  211. vco = (u64)ls_freq * settings->hs_div;
  212. /* Calculate the integer part of the feedback divider */
  213. tmp = do_div(vco, FXO);
  214. settings->fb_div_int = vco;
  215. /* And the fractional bits using the remainder */
  216. vco = (u64)tmp << 32;
  217. vco += FXO / 2; /* Round to nearest multiple */
  218. do_div(vco, FXO);
  219. settings->fb_div_frac = vco;
  220. /* Reset the frequency adjustment */
  221. settings->delta_m = 0;
  222. return 0;
  223. }
  224. /* Calculate resulting frequency given the register settings */
  225. static unsigned long si544_calc_center_rate(
  226. const struct clk_si544_muldiv *settings)
  227. {
  228. u32 d = settings->hs_div * BIT(settings->ls_div_bits);
  229. u64 vco;
  230. /* Calculate VCO from the fractional part */
  231. vco = (u64)settings->fb_div_frac * FXO;
  232. vco += (FXO / 2);
  233. vco >>= 32;
  234. /* Add the integer part of the VCO frequency */
  235. vco += (u64)settings->fb_div_int * FXO;
  236. /* Apply divider to obtain the generated frequency */
  237. do_div(vco, d);
  238. return vco;
  239. }
  240. static unsigned long si544_calc_rate(const struct clk_si544_muldiv *settings)
  241. {
  242. unsigned long rate = si544_calc_center_rate(settings);
  243. s64 delta = (s64)rate * (DELTA_M_FRAC_NUM * settings->delta_m);
  244. /*
  245. * The clock adjustment is much smaller than 1 Hz, round to the
  246. * nearest multiple. Apparently div64_s64 rounds towards zero, hence
  247. * check the sign and adjust into the proper direction.
  248. */
  249. if (settings->delta_m < 0)
  250. delta -= ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN) / 2;
  251. else
  252. delta += ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN) / 2;
  253. delta = div64_s64(delta, ((s64)DELTA_M_MAX * DELTA_M_FRAC_DEN));
  254. return rate + delta;
  255. }
  256. static unsigned long si544_recalc_rate(struct clk_hw *hw,
  257. unsigned long parent_rate)
  258. {
  259. struct clk_si544 *data = to_clk_si544(hw);
  260. struct clk_si544_muldiv settings;
  261. int err;
  262. err = si544_get_muldiv(data, &settings);
  263. if (err)
  264. return 0;
  265. return si544_calc_rate(&settings);
  266. }
  267. static long si544_round_rate(struct clk_hw *hw, unsigned long rate,
  268. unsigned long *parent_rate)
  269. {
  270. struct clk_si544 *data = to_clk_si544(hw);
  271. if (!is_valid_frequency(data, rate))
  272. return -EINVAL;
  273. /* The accuracy is less than 1 Hz, so any rate is possible */
  274. return rate;
  275. }
  276. /* Calculates the maximum "small" change, 950 * rate / 1000000 */
  277. static unsigned long si544_max_delta(unsigned long rate)
  278. {
  279. u64 num = rate;
  280. num *= DELTA_M_FRAC_NUM;
  281. do_div(num, DELTA_M_FRAC_DEN);
  282. return num;
  283. }
  284. static s32 si544_calc_delta(s32 delta, s32 max_delta)
  285. {
  286. s64 n = (s64)delta * DELTA_M_MAX;
  287. return div_s64(n, max_delta);
  288. }
  289. static int si544_set_rate(struct clk_hw *hw, unsigned long rate,
  290. unsigned long parent_rate)
  291. {
  292. struct clk_si544 *data = to_clk_si544(hw);
  293. struct clk_si544_muldiv settings;
  294. unsigned long center;
  295. long max_delta;
  296. long delta;
  297. unsigned int old_oe_state;
  298. int err;
  299. if (!is_valid_frequency(data, rate))
  300. return -EINVAL;
  301. /* Try using the frequency adjustment feature for a <= 950ppm change */
  302. err = si544_get_muldiv(data, &settings);
  303. if (err)
  304. return err;
  305. center = si544_calc_center_rate(&settings);
  306. max_delta = si544_max_delta(center);
  307. delta = rate - center;
  308. if (abs(delta) <= max_delta)
  309. return si544_set_delta_m(data,
  310. si544_calc_delta(delta, max_delta));
  311. /* Too big for the delta adjustment, need to reprogram */
  312. err = si544_calc_muldiv(&settings, rate);
  313. if (err)
  314. return err;
  315. err = regmap_read(data->regmap, SI544_REG_OE_STATE, &old_oe_state);
  316. if (err)
  317. return err;
  318. si544_enable_output(data, false);
  319. /* Allow FCAL for this frequency update */
  320. err = regmap_write(data->regmap, SI544_REG_FCAL_OVR, 0);
  321. if (err < 0)
  322. return err;
  323. err = si544_set_delta_m(data, settings.delta_m);
  324. if (err < 0)
  325. return err;
  326. err = si544_set_muldiv(data, &settings);
  327. if (err < 0)
  328. return err; /* Undefined state now, best to leave disabled */
  329. /* Trigger calibration */
  330. err = regmap_write(data->regmap, SI544_REG_CONTROL,
  331. SI544_CONTROL_MS_ICAL2);
  332. if (err < 0)
  333. return err;
  334. /* Applying a new frequency can take up to 10ms */
  335. usleep_range(10000, 12000);
  336. if (old_oe_state & SI544_OE_STATE_ODC_OE)
  337. si544_enable_output(data, true);
  338. return err;
  339. }
  340. static const struct clk_ops si544_clk_ops = {
  341. .prepare = si544_prepare,
  342. .unprepare = si544_unprepare,
  343. .is_prepared = si544_is_prepared,
  344. .recalc_rate = si544_recalc_rate,
  345. .round_rate = si544_round_rate,
  346. .set_rate = si544_set_rate,
  347. };
  348. static bool si544_regmap_is_volatile(struct device *dev, unsigned int reg)
  349. {
  350. switch (reg) {
  351. case SI544_REG_CONTROL:
  352. case SI544_REG_FCAL_OVR:
  353. return true;
  354. default:
  355. return false;
  356. }
  357. }
  358. static const struct regmap_config si544_regmap_config = {
  359. .reg_bits = 8,
  360. .val_bits = 8,
  361. .cache_type = REGCACHE_RBTREE,
  362. .max_register = SI544_REG_PAGE_SELECT,
  363. .volatile_reg = si544_regmap_is_volatile,
  364. };
  365. static int si544_probe(struct i2c_client *client,
  366. const struct i2c_device_id *id)
  367. {
  368. struct clk_si544 *data;
  369. struct clk_init_data init;
  370. int err;
  371. data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
  372. if (!data)
  373. return -ENOMEM;
  374. init.ops = &si544_clk_ops;
  375. init.flags = 0;
  376. init.num_parents = 0;
  377. data->hw.init = &init;
  378. data->i2c_client = client;
  379. data->speed_grade = id->driver_data;
  380. if (of_property_read_string(client->dev.of_node, "clock-output-names",
  381. &init.name))
  382. init.name = client->dev.of_node->name;
  383. data->regmap = devm_regmap_init_i2c(client, &si544_regmap_config);
  384. if (IS_ERR(data->regmap))
  385. return PTR_ERR(data->regmap);
  386. i2c_set_clientdata(client, data);
  387. /* Select page 0, just to be sure, there appear to be no more */
  388. err = regmap_write(data->regmap, SI544_REG_PAGE_SELECT, 0);
  389. if (err < 0)
  390. return err;
  391. err = devm_clk_hw_register(&client->dev, &data->hw);
  392. if (err) {
  393. dev_err(&client->dev, "clock registration failed\n");
  394. return err;
  395. }
  396. err = devm_of_clk_add_hw_provider(&client->dev, of_clk_hw_simple_get,
  397. &data->hw);
  398. if (err) {
  399. dev_err(&client->dev, "unable to add clk provider\n");
  400. return err;
  401. }
  402. return 0;
  403. }
  404. static const struct i2c_device_id si544_id[] = {
  405. { "si544a", si544a },
  406. { "si544b", si544b },
  407. { "si544c", si544c },
  408. { }
  409. };
  410. MODULE_DEVICE_TABLE(i2c, si544_id);
  411. static const struct of_device_id clk_si544_of_match[] = {
  412. { .compatible = "silabs,si544a" },
  413. { .compatible = "silabs,si544b" },
  414. { .compatible = "silabs,si544c" },
  415. { },
  416. };
  417. MODULE_DEVICE_TABLE(of, clk_si544_of_match);
  418. static struct i2c_driver si544_driver = {
  419. .driver = {
  420. .name = "si544",
  421. .of_match_table = clk_si544_of_match,
  422. },
  423. .probe = si544_probe,
  424. .id_table = si544_id,
  425. };
  426. module_i2c_driver(si544_driver);
  427. MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
  428. MODULE_DESCRIPTION("Si544 driver");
  429. MODULE_LICENSE("GPL");