clk-si5351.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
  4. *
  5. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  6. * Rabeeh Khoury <rabeeh@solid-run.com>
  7. *
  8. * References:
  9. * [1] "Si5351A/B/C Data Sheet"
  10. * https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
  11. * [2] "Manually Generating an Si5351 Register Map"
  12. * https://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/clk.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. #include <linux/errno.h>
  21. #include <linux/rational.h>
  22. #include <linux/i2c.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/platform_data/si5351.h>
  25. #include <linux/regmap.h>
  26. #include <linux/slab.h>
  27. #include <linux/string.h>
  28. #include <asm/div64.h>
  29. #include "clk-si5351.h"
  30. struct si5351_driver_data;
  31. struct si5351_parameters {
  32. unsigned long p1;
  33. unsigned long p2;
  34. unsigned long p3;
  35. int valid;
  36. };
  37. struct si5351_hw_data {
  38. struct clk_hw hw;
  39. struct si5351_driver_data *drvdata;
  40. struct si5351_parameters params;
  41. unsigned char num;
  42. };
  43. struct si5351_driver_data {
  44. enum si5351_variant variant;
  45. struct i2c_client *client;
  46. struct regmap *regmap;
  47. struct clk *pxtal;
  48. const char *pxtal_name;
  49. struct clk_hw xtal;
  50. struct clk *pclkin;
  51. const char *pclkin_name;
  52. struct clk_hw clkin;
  53. struct si5351_hw_data pll[2];
  54. struct si5351_hw_data *msynth;
  55. struct si5351_hw_data *clkout;
  56. size_t num_clkout;
  57. };
  58. static const char * const si5351_input_names[] = {
  59. "xtal", "clkin"
  60. };
  61. static const char * const si5351_pll_names[] = {
  62. "si5351_plla", "si5351_pllb", "si5351_vxco"
  63. };
  64. static const char * const si5351_msynth_names[] = {
  65. "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
  66. };
  67. static const char * const si5351_clkout_names[] = {
  68. "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
  69. };
  70. /*
  71. * Si5351 i2c regmap
  72. */
  73. static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
  74. {
  75. u32 val;
  76. int ret;
  77. ret = regmap_read(drvdata->regmap, reg, &val);
  78. if (ret) {
  79. dev_err(&drvdata->client->dev,
  80. "unable to read from reg%02x\n", reg);
  81. return 0;
  82. }
  83. return (u8)val;
  84. }
  85. static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
  86. u8 reg, u8 count, u8 *buf)
  87. {
  88. return regmap_bulk_read(drvdata->regmap, reg, buf, count);
  89. }
  90. static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
  91. u8 reg, u8 val)
  92. {
  93. return regmap_write(drvdata->regmap, reg, val);
  94. }
  95. static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
  96. u8 reg, u8 count, const u8 *buf)
  97. {
  98. return regmap_raw_write(drvdata->regmap, reg, buf, count);
  99. }
  100. static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
  101. u8 reg, u8 mask, u8 val)
  102. {
  103. return regmap_update_bits(drvdata->regmap, reg, mask, val);
  104. }
  105. static inline u8 si5351_msynth_params_address(int num)
  106. {
  107. if (num > 5)
  108. return SI5351_CLK6_PARAMETERS + (num - 6);
  109. return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
  110. }
  111. static void si5351_read_parameters(struct si5351_driver_data *drvdata,
  112. u8 reg, struct si5351_parameters *params)
  113. {
  114. u8 buf[SI5351_PARAMETERS_LENGTH];
  115. switch (reg) {
  116. case SI5351_CLK6_PARAMETERS:
  117. case SI5351_CLK7_PARAMETERS:
  118. buf[0] = si5351_reg_read(drvdata, reg);
  119. params->p1 = buf[0];
  120. params->p2 = 0;
  121. params->p3 = 1;
  122. break;
  123. default:
  124. si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
  125. params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
  126. params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
  127. params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
  128. }
  129. params->valid = 1;
  130. }
  131. static void si5351_write_parameters(struct si5351_driver_data *drvdata,
  132. u8 reg, struct si5351_parameters *params)
  133. {
  134. u8 buf[SI5351_PARAMETERS_LENGTH];
  135. switch (reg) {
  136. case SI5351_CLK6_PARAMETERS:
  137. case SI5351_CLK7_PARAMETERS:
  138. buf[0] = params->p1 & 0xff;
  139. si5351_reg_write(drvdata, reg, buf[0]);
  140. break;
  141. default:
  142. buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
  143. buf[1] = params->p3 & 0xff;
  144. /* save rdiv and divby4 */
  145. buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
  146. buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
  147. buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
  148. buf[4] = params->p1 & 0xff;
  149. buf[5] = ((params->p3 & 0xf0000) >> 12) |
  150. ((params->p2 & 0xf0000) >> 16);
  151. buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
  152. buf[7] = params->p2 & 0xff;
  153. si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
  154. }
  155. }
  156. static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
  157. {
  158. switch (reg) {
  159. case SI5351_DEVICE_STATUS:
  160. case SI5351_INTERRUPT_STATUS:
  161. case SI5351_PLL_RESET:
  162. return true;
  163. }
  164. return false;
  165. }
  166. static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
  167. {
  168. /* reserved registers */
  169. if (reg >= 4 && reg <= 8)
  170. return false;
  171. if (reg >= 10 && reg <= 14)
  172. return false;
  173. if (reg >= 173 && reg <= 176)
  174. return false;
  175. if (reg >= 178 && reg <= 182)
  176. return false;
  177. /* read-only */
  178. if (reg == SI5351_DEVICE_STATUS)
  179. return false;
  180. return true;
  181. }
  182. static const struct regmap_config si5351_regmap_config = {
  183. .reg_bits = 8,
  184. .val_bits = 8,
  185. .cache_type = REGCACHE_RBTREE,
  186. .max_register = 187,
  187. .writeable_reg = si5351_regmap_is_writeable,
  188. .volatile_reg = si5351_regmap_is_volatile,
  189. };
  190. /*
  191. * Si5351 xtal clock input
  192. */
  193. static int si5351_xtal_prepare(struct clk_hw *hw)
  194. {
  195. struct si5351_driver_data *drvdata =
  196. container_of(hw, struct si5351_driver_data, xtal);
  197. si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
  198. SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
  199. return 0;
  200. }
  201. static void si5351_xtal_unprepare(struct clk_hw *hw)
  202. {
  203. struct si5351_driver_data *drvdata =
  204. container_of(hw, struct si5351_driver_data, xtal);
  205. si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
  206. SI5351_XTAL_ENABLE, 0);
  207. }
  208. static const struct clk_ops si5351_xtal_ops = {
  209. .prepare = si5351_xtal_prepare,
  210. .unprepare = si5351_xtal_unprepare,
  211. };
  212. /*
  213. * Si5351 clkin clock input (Si5351C only)
  214. */
  215. static int si5351_clkin_prepare(struct clk_hw *hw)
  216. {
  217. struct si5351_driver_data *drvdata =
  218. container_of(hw, struct si5351_driver_data, clkin);
  219. si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
  220. SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
  221. return 0;
  222. }
  223. static void si5351_clkin_unprepare(struct clk_hw *hw)
  224. {
  225. struct si5351_driver_data *drvdata =
  226. container_of(hw, struct si5351_driver_data, clkin);
  227. si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
  228. SI5351_CLKIN_ENABLE, 0);
  229. }
  230. /*
  231. * CMOS clock source constraints:
  232. * The input frequency range of the PLL is 10Mhz to 40MHz.
  233. * If CLKIN is >40MHz, the input divider must be used.
  234. */
  235. static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
  236. unsigned long parent_rate)
  237. {
  238. struct si5351_driver_data *drvdata =
  239. container_of(hw, struct si5351_driver_data, clkin);
  240. unsigned long rate;
  241. unsigned char idiv;
  242. rate = parent_rate;
  243. if (parent_rate > 160000000) {
  244. idiv = SI5351_CLKIN_DIV_8;
  245. rate /= 8;
  246. } else if (parent_rate > 80000000) {
  247. idiv = SI5351_CLKIN_DIV_4;
  248. rate /= 4;
  249. } else if (parent_rate > 40000000) {
  250. idiv = SI5351_CLKIN_DIV_2;
  251. rate /= 2;
  252. } else {
  253. idiv = SI5351_CLKIN_DIV_1;
  254. }
  255. si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
  256. SI5351_CLKIN_DIV_MASK, idiv);
  257. dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
  258. __func__, (1 << (idiv >> 6)), rate);
  259. return rate;
  260. }
  261. static const struct clk_ops si5351_clkin_ops = {
  262. .prepare = si5351_clkin_prepare,
  263. .unprepare = si5351_clkin_unprepare,
  264. .recalc_rate = si5351_clkin_recalc_rate,
  265. };
  266. /*
  267. * Si5351 vxco clock input (Si5351B only)
  268. */
  269. static int si5351_vxco_prepare(struct clk_hw *hw)
  270. {
  271. struct si5351_hw_data *hwdata =
  272. container_of(hw, struct si5351_hw_data, hw);
  273. dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
  274. return 0;
  275. }
  276. static void si5351_vxco_unprepare(struct clk_hw *hw)
  277. {
  278. }
  279. static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
  280. unsigned long parent_rate)
  281. {
  282. return 0;
  283. }
  284. static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
  285. unsigned long parent)
  286. {
  287. return 0;
  288. }
  289. static const struct clk_ops si5351_vxco_ops = {
  290. .prepare = si5351_vxco_prepare,
  291. .unprepare = si5351_vxco_unprepare,
  292. .recalc_rate = si5351_vxco_recalc_rate,
  293. .set_rate = si5351_vxco_set_rate,
  294. };
  295. /*
  296. * Si5351 pll a/b
  297. *
  298. * Feedback Multisynth Divider Equations [2]
  299. *
  300. * fVCO = fIN * (a + b/c)
  301. *
  302. * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
  303. * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
  304. *
  305. * Feedback Multisynth Register Equations
  306. *
  307. * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
  308. * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
  309. * (3) MSNx_P3[19:0] = c
  310. *
  311. * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
  312. *
  313. * Using (4) on (1) yields:
  314. * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
  315. * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
  316. *
  317. * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
  318. * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
  319. *
  320. */
  321. static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
  322. int num, enum si5351_pll_src parent)
  323. {
  324. u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
  325. if (parent == SI5351_PLL_SRC_DEFAULT)
  326. return 0;
  327. if (num > 2)
  328. return -EINVAL;
  329. if (drvdata->variant != SI5351_VARIANT_C &&
  330. parent != SI5351_PLL_SRC_XTAL)
  331. return -EINVAL;
  332. si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
  333. (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
  334. return 0;
  335. }
  336. static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
  337. {
  338. struct si5351_hw_data *hwdata =
  339. container_of(hw, struct si5351_hw_data, hw);
  340. u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
  341. u8 val;
  342. val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
  343. return (val & mask) ? 1 : 0;
  344. }
  345. static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
  346. {
  347. struct si5351_hw_data *hwdata =
  348. container_of(hw, struct si5351_hw_data, hw);
  349. if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
  350. index > 0)
  351. return -EPERM;
  352. if (index > 1)
  353. return -EINVAL;
  354. return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
  355. (index == 0) ? SI5351_PLL_SRC_XTAL :
  356. SI5351_PLL_SRC_CLKIN);
  357. }
  358. static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
  359. unsigned long parent_rate)
  360. {
  361. struct si5351_hw_data *hwdata =
  362. container_of(hw, struct si5351_hw_data, hw);
  363. u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
  364. SI5351_PLLB_PARAMETERS;
  365. unsigned long long rate;
  366. if (!hwdata->params.valid)
  367. si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
  368. if (hwdata->params.p3 == 0)
  369. return parent_rate;
  370. /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
  371. rate = hwdata->params.p1 * hwdata->params.p3;
  372. rate += 512 * hwdata->params.p3;
  373. rate += hwdata->params.p2;
  374. rate *= parent_rate;
  375. do_div(rate, 128 * hwdata->params.p3);
  376. dev_dbg(&hwdata->drvdata->client->dev,
  377. "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
  378. __func__, clk_hw_get_name(hw),
  379. hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
  380. parent_rate, (unsigned long)rate);
  381. return (unsigned long)rate;
  382. }
  383. static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  384. unsigned long *parent_rate)
  385. {
  386. struct si5351_hw_data *hwdata =
  387. container_of(hw, struct si5351_hw_data, hw);
  388. unsigned long rfrac, denom, a, b, c;
  389. unsigned long long lltmp;
  390. if (rate < SI5351_PLL_VCO_MIN)
  391. rate = SI5351_PLL_VCO_MIN;
  392. if (rate > SI5351_PLL_VCO_MAX)
  393. rate = SI5351_PLL_VCO_MAX;
  394. /* determine integer part of feedback equation */
  395. a = rate / *parent_rate;
  396. if (a < SI5351_PLL_A_MIN)
  397. rate = *parent_rate * SI5351_PLL_A_MIN;
  398. if (a > SI5351_PLL_A_MAX)
  399. rate = *parent_rate * SI5351_PLL_A_MAX;
  400. /* find best approximation for b/c = fVCO mod fIN */
  401. denom = 1000 * 1000;
  402. lltmp = rate % (*parent_rate);
  403. lltmp *= denom;
  404. do_div(lltmp, *parent_rate);
  405. rfrac = (unsigned long)lltmp;
  406. b = 0;
  407. c = 1;
  408. if (rfrac)
  409. rational_best_approximation(rfrac, denom,
  410. SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
  411. /* calculate parameters */
  412. hwdata->params.p3 = c;
  413. hwdata->params.p2 = (128 * b) % c;
  414. hwdata->params.p1 = 128 * a;
  415. hwdata->params.p1 += (128 * b / c);
  416. hwdata->params.p1 -= 512;
  417. /* recalculate rate by fIN * (a + b/c) */
  418. lltmp = *parent_rate;
  419. lltmp *= b;
  420. do_div(lltmp, c);
  421. rate = (unsigned long)lltmp;
  422. rate += *parent_rate * a;
  423. dev_dbg(&hwdata->drvdata->client->dev,
  424. "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
  425. __func__, clk_hw_get_name(hw), a, b, c,
  426. *parent_rate, rate);
  427. return rate;
  428. }
  429. static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  430. unsigned long parent_rate)
  431. {
  432. struct si5351_hw_data *hwdata =
  433. container_of(hw, struct si5351_hw_data, hw);
  434. u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
  435. SI5351_PLLB_PARAMETERS;
  436. /* write multisynth parameters */
  437. si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
  438. /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
  439. si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
  440. SI5351_CLK_INTEGER_MODE,
  441. (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
  442. /* Do a pll soft reset on the affected pll */
  443. si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
  444. hwdata->num == 0 ? SI5351_PLL_RESET_A :
  445. SI5351_PLL_RESET_B);
  446. dev_dbg(&hwdata->drvdata->client->dev,
  447. "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
  448. __func__, clk_hw_get_name(hw),
  449. hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
  450. parent_rate, rate);
  451. return 0;
  452. }
  453. static const struct clk_ops si5351_pll_ops = {
  454. .set_parent = si5351_pll_set_parent,
  455. .get_parent = si5351_pll_get_parent,
  456. .recalc_rate = si5351_pll_recalc_rate,
  457. .round_rate = si5351_pll_round_rate,
  458. .set_rate = si5351_pll_set_rate,
  459. };
  460. /*
  461. * Si5351 multisync divider
  462. *
  463. * for fOUT <= 150 MHz:
  464. *
  465. * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
  466. *
  467. * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
  468. * fIN = fVCO0, fVCO1
  469. *
  470. * Output Clock Multisynth Register Equations
  471. *
  472. * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
  473. * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
  474. * MSx_P3[19:0] = c
  475. *
  476. * MS[6,7] are integer (P1) divide only, P1 = divide value,
  477. * P2 and P3 are not applicable
  478. *
  479. * for 150MHz < fOUT <= 160MHz:
  480. *
  481. * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
  482. */
  483. static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
  484. int num, enum si5351_multisynth_src parent)
  485. {
  486. if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
  487. return 0;
  488. if (num > 8)
  489. return -EINVAL;
  490. si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
  491. (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
  492. SI5351_CLK_PLL_SELECT);
  493. return 0;
  494. }
  495. static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
  496. {
  497. struct si5351_hw_data *hwdata =
  498. container_of(hw, struct si5351_hw_data, hw);
  499. u8 val;
  500. val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
  501. return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
  502. }
  503. static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
  504. {
  505. struct si5351_hw_data *hwdata =
  506. container_of(hw, struct si5351_hw_data, hw);
  507. return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
  508. (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
  509. SI5351_MULTISYNTH_SRC_VCO1);
  510. }
  511. static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
  512. unsigned long parent_rate)
  513. {
  514. struct si5351_hw_data *hwdata =
  515. container_of(hw, struct si5351_hw_data, hw);
  516. u8 reg = si5351_msynth_params_address(hwdata->num);
  517. unsigned long long rate;
  518. unsigned long m;
  519. if (!hwdata->params.valid)
  520. si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
  521. /*
  522. * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
  523. * multisync6-7: fOUT = fIN / P1
  524. */
  525. rate = parent_rate;
  526. if (hwdata->num > 5) {
  527. m = hwdata->params.p1;
  528. } else if (hwdata->params.p3 == 0) {
  529. return parent_rate;
  530. } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
  531. SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
  532. m = 4;
  533. } else {
  534. rate *= 128 * hwdata->params.p3;
  535. m = hwdata->params.p1 * hwdata->params.p3;
  536. m += hwdata->params.p2;
  537. m += 512 * hwdata->params.p3;
  538. }
  539. if (m == 0)
  540. return 0;
  541. do_div(rate, m);
  542. dev_dbg(&hwdata->drvdata->client->dev,
  543. "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
  544. __func__, clk_hw_get_name(hw),
  545. hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
  546. m, parent_rate, (unsigned long)rate);
  547. return (unsigned long)rate;
  548. }
  549. static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
  550. unsigned long *parent_rate)
  551. {
  552. struct si5351_hw_data *hwdata =
  553. container_of(hw, struct si5351_hw_data, hw);
  554. unsigned long long lltmp;
  555. unsigned long a, b, c;
  556. int divby4;
  557. /* multisync6-7 can only handle freqencies < 150MHz */
  558. if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
  559. rate = SI5351_MULTISYNTH67_MAX_FREQ;
  560. /* multisync frequency is 1MHz .. 160MHz */
  561. if (rate > SI5351_MULTISYNTH_MAX_FREQ)
  562. rate = SI5351_MULTISYNTH_MAX_FREQ;
  563. if (rate < SI5351_MULTISYNTH_MIN_FREQ)
  564. rate = SI5351_MULTISYNTH_MIN_FREQ;
  565. divby4 = 0;
  566. if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
  567. divby4 = 1;
  568. /* multisync can set pll */
  569. if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  570. /*
  571. * find largest integer divider for max
  572. * vco frequency and given target rate
  573. */
  574. if (divby4 == 0) {
  575. lltmp = SI5351_PLL_VCO_MAX;
  576. do_div(lltmp, rate);
  577. a = (unsigned long)lltmp;
  578. } else
  579. a = 4;
  580. b = 0;
  581. c = 1;
  582. *parent_rate = a * rate;
  583. } else if (hwdata->num >= 6) {
  584. /* determine the closest integer divider */
  585. a = DIV_ROUND_CLOSEST(*parent_rate, rate);
  586. if (a < SI5351_MULTISYNTH_A_MIN)
  587. a = SI5351_MULTISYNTH_A_MIN;
  588. if (a > SI5351_MULTISYNTH67_A_MAX)
  589. a = SI5351_MULTISYNTH67_A_MAX;
  590. b = 0;
  591. c = 1;
  592. } else {
  593. unsigned long rfrac, denom;
  594. /* disable divby4 */
  595. if (divby4) {
  596. rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
  597. divby4 = 0;
  598. }
  599. /* determine integer part of divider equation */
  600. a = *parent_rate / rate;
  601. if (a < SI5351_MULTISYNTH_A_MIN)
  602. a = SI5351_MULTISYNTH_A_MIN;
  603. if (a > SI5351_MULTISYNTH_A_MAX)
  604. a = SI5351_MULTISYNTH_A_MAX;
  605. /* find best approximation for b/c = fVCO mod fOUT */
  606. denom = 1000 * 1000;
  607. lltmp = (*parent_rate) % rate;
  608. lltmp *= denom;
  609. do_div(lltmp, rate);
  610. rfrac = (unsigned long)lltmp;
  611. b = 0;
  612. c = 1;
  613. if (rfrac)
  614. rational_best_approximation(rfrac, denom,
  615. SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
  616. &b, &c);
  617. }
  618. /* recalculate rate by fOUT = fIN / (a + b/c) */
  619. lltmp = *parent_rate;
  620. lltmp *= c;
  621. do_div(lltmp, a * c + b);
  622. rate = (unsigned long)lltmp;
  623. /* calculate parameters */
  624. if (divby4) {
  625. hwdata->params.p3 = 1;
  626. hwdata->params.p2 = 0;
  627. hwdata->params.p1 = 0;
  628. } else if (hwdata->num >= 6) {
  629. hwdata->params.p3 = 0;
  630. hwdata->params.p2 = 0;
  631. hwdata->params.p1 = a;
  632. } else {
  633. hwdata->params.p3 = c;
  634. hwdata->params.p2 = (128 * b) % c;
  635. hwdata->params.p1 = 128 * a;
  636. hwdata->params.p1 += (128 * b / c);
  637. hwdata->params.p1 -= 512;
  638. }
  639. dev_dbg(&hwdata->drvdata->client->dev,
  640. "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
  641. __func__, clk_hw_get_name(hw), a, b, c, divby4,
  642. *parent_rate, rate);
  643. return rate;
  644. }
  645. static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
  646. unsigned long parent_rate)
  647. {
  648. struct si5351_hw_data *hwdata =
  649. container_of(hw, struct si5351_hw_data, hw);
  650. u8 reg = si5351_msynth_params_address(hwdata->num);
  651. int divby4 = 0;
  652. /* write multisynth parameters */
  653. si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
  654. if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
  655. divby4 = 1;
  656. /* enable/disable integer mode and divby4 on multisynth0-5 */
  657. if (hwdata->num < 6) {
  658. si5351_set_bits(hwdata->drvdata, reg + 2,
  659. SI5351_OUTPUT_CLK_DIVBY4,
  660. (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
  661. si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
  662. SI5351_CLK_INTEGER_MODE,
  663. (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
  664. }
  665. dev_dbg(&hwdata->drvdata->client->dev,
  666. "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
  667. __func__, clk_hw_get_name(hw),
  668. hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
  669. divby4, parent_rate, rate);
  670. return 0;
  671. }
  672. static const struct clk_ops si5351_msynth_ops = {
  673. .set_parent = si5351_msynth_set_parent,
  674. .get_parent = si5351_msynth_get_parent,
  675. .recalc_rate = si5351_msynth_recalc_rate,
  676. .round_rate = si5351_msynth_round_rate,
  677. .set_rate = si5351_msynth_set_rate,
  678. };
  679. /*
  680. * Si5351 clkout divider
  681. */
  682. static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
  683. int num, enum si5351_clkout_src parent)
  684. {
  685. u8 val;
  686. if (num > 8)
  687. return -EINVAL;
  688. switch (parent) {
  689. case SI5351_CLKOUT_SRC_MSYNTH_N:
  690. val = SI5351_CLK_INPUT_MULTISYNTH_N;
  691. break;
  692. case SI5351_CLKOUT_SRC_MSYNTH_0_4:
  693. /* clk0/clk4 can only connect to its own multisync */
  694. if (num == 0 || num == 4)
  695. val = SI5351_CLK_INPUT_MULTISYNTH_N;
  696. else
  697. val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
  698. break;
  699. case SI5351_CLKOUT_SRC_XTAL:
  700. val = SI5351_CLK_INPUT_XTAL;
  701. break;
  702. case SI5351_CLKOUT_SRC_CLKIN:
  703. if (drvdata->variant != SI5351_VARIANT_C)
  704. return -EINVAL;
  705. val = SI5351_CLK_INPUT_CLKIN;
  706. break;
  707. default:
  708. return 0;
  709. }
  710. si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
  711. SI5351_CLK_INPUT_MASK, val);
  712. return 0;
  713. }
  714. static int _si5351_clkout_set_drive_strength(
  715. struct si5351_driver_data *drvdata, int num,
  716. enum si5351_drive_strength drive)
  717. {
  718. u8 mask;
  719. if (num > 8)
  720. return -EINVAL;
  721. switch (drive) {
  722. case SI5351_DRIVE_2MA:
  723. mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
  724. break;
  725. case SI5351_DRIVE_4MA:
  726. mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
  727. break;
  728. case SI5351_DRIVE_6MA:
  729. mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
  730. break;
  731. case SI5351_DRIVE_8MA:
  732. mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
  733. break;
  734. default:
  735. return 0;
  736. }
  737. si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
  738. SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
  739. return 0;
  740. }
  741. static int _si5351_clkout_set_disable_state(
  742. struct si5351_driver_data *drvdata, int num,
  743. enum si5351_disable_state state)
  744. {
  745. u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
  746. SI5351_CLK7_4_DISABLE_STATE;
  747. u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
  748. u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
  749. u8 val;
  750. if (num > 8)
  751. return -EINVAL;
  752. switch (state) {
  753. case SI5351_DISABLE_LOW:
  754. val = SI5351_CLK_DISABLE_STATE_LOW;
  755. break;
  756. case SI5351_DISABLE_HIGH:
  757. val = SI5351_CLK_DISABLE_STATE_HIGH;
  758. break;
  759. case SI5351_DISABLE_FLOATING:
  760. val = SI5351_CLK_DISABLE_STATE_FLOAT;
  761. break;
  762. case SI5351_DISABLE_NEVER:
  763. val = SI5351_CLK_DISABLE_STATE_NEVER;
  764. break;
  765. default:
  766. return 0;
  767. }
  768. si5351_set_bits(drvdata, reg, mask, val << shift);
  769. return 0;
  770. }
  771. static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
  772. {
  773. u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
  774. switch (val & SI5351_CLK_INPUT_MASK) {
  775. case SI5351_CLK_INPUT_XTAL:
  776. case SI5351_CLK_INPUT_CLKIN:
  777. return; /* pll not used, no need to reset */
  778. }
  779. si5351_reg_write(drvdata, SI5351_PLL_RESET,
  780. val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
  781. SI5351_PLL_RESET_A);
  782. dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
  783. __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
  784. (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
  785. }
  786. static int si5351_clkout_prepare(struct clk_hw *hw)
  787. {
  788. struct si5351_hw_data *hwdata =
  789. container_of(hw, struct si5351_hw_data, hw);
  790. struct si5351_platform_data *pdata =
  791. hwdata->drvdata->client->dev.platform_data;
  792. si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
  793. SI5351_CLK_POWERDOWN, 0);
  794. /*
  795. * Do a pll soft reset on the parent pll -- needed to get a
  796. * deterministic phase relationship between the output clocks.
  797. */
  798. if (pdata->clkout[hwdata->num].pll_reset)
  799. _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
  800. si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
  801. (1 << hwdata->num), 0);
  802. return 0;
  803. }
  804. static void si5351_clkout_unprepare(struct clk_hw *hw)
  805. {
  806. struct si5351_hw_data *hwdata =
  807. container_of(hw, struct si5351_hw_data, hw);
  808. si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
  809. SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
  810. si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
  811. (1 << hwdata->num), (1 << hwdata->num));
  812. }
  813. static u8 si5351_clkout_get_parent(struct clk_hw *hw)
  814. {
  815. struct si5351_hw_data *hwdata =
  816. container_of(hw, struct si5351_hw_data, hw);
  817. int index = 0;
  818. unsigned char val;
  819. val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
  820. switch (val & SI5351_CLK_INPUT_MASK) {
  821. case SI5351_CLK_INPUT_MULTISYNTH_N:
  822. index = 0;
  823. break;
  824. case SI5351_CLK_INPUT_MULTISYNTH_0_4:
  825. index = 1;
  826. break;
  827. case SI5351_CLK_INPUT_XTAL:
  828. index = 2;
  829. break;
  830. case SI5351_CLK_INPUT_CLKIN:
  831. index = 3;
  832. break;
  833. }
  834. return index;
  835. }
  836. static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
  837. {
  838. struct si5351_hw_data *hwdata =
  839. container_of(hw, struct si5351_hw_data, hw);
  840. enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
  841. switch (index) {
  842. case 0:
  843. parent = SI5351_CLKOUT_SRC_MSYNTH_N;
  844. break;
  845. case 1:
  846. parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
  847. break;
  848. case 2:
  849. parent = SI5351_CLKOUT_SRC_XTAL;
  850. break;
  851. case 3:
  852. parent = SI5351_CLKOUT_SRC_CLKIN;
  853. break;
  854. }
  855. return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
  856. }
  857. static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
  858. unsigned long parent_rate)
  859. {
  860. struct si5351_hw_data *hwdata =
  861. container_of(hw, struct si5351_hw_data, hw);
  862. unsigned char reg;
  863. unsigned char rdiv;
  864. if (hwdata->num <= 5)
  865. reg = si5351_msynth_params_address(hwdata->num) + 2;
  866. else
  867. reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
  868. rdiv = si5351_reg_read(hwdata->drvdata, reg);
  869. if (hwdata->num == 6) {
  870. rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
  871. } else {
  872. rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
  873. rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
  874. }
  875. return parent_rate >> rdiv;
  876. }
  877. static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
  878. unsigned long *parent_rate)
  879. {
  880. struct si5351_hw_data *hwdata =
  881. container_of(hw, struct si5351_hw_data, hw);
  882. unsigned char rdiv;
  883. /* clkout6/7 can only handle output freqencies < 150MHz */
  884. if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
  885. rate = SI5351_CLKOUT67_MAX_FREQ;
  886. /* clkout freqency is 8kHz - 160MHz */
  887. if (rate > SI5351_CLKOUT_MAX_FREQ)
  888. rate = SI5351_CLKOUT_MAX_FREQ;
  889. if (rate < SI5351_CLKOUT_MIN_FREQ)
  890. rate = SI5351_CLKOUT_MIN_FREQ;
  891. /* request frequency if multisync master */
  892. if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  893. /* use r divider for frequencies below 1MHz */
  894. rdiv = SI5351_OUTPUT_CLK_DIV_1;
  895. while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
  896. rdiv < SI5351_OUTPUT_CLK_DIV_128) {
  897. rdiv += 1;
  898. rate *= 2;
  899. }
  900. *parent_rate = rate;
  901. } else {
  902. unsigned long new_rate, new_err, err;
  903. /* round to closed rdiv */
  904. rdiv = SI5351_OUTPUT_CLK_DIV_1;
  905. new_rate = *parent_rate;
  906. err = abs(new_rate - rate);
  907. do {
  908. new_rate >>= 1;
  909. new_err = abs(new_rate - rate);
  910. if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
  911. break;
  912. rdiv++;
  913. err = new_err;
  914. } while (1);
  915. }
  916. rate = *parent_rate >> rdiv;
  917. dev_dbg(&hwdata->drvdata->client->dev,
  918. "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
  919. __func__, clk_hw_get_name(hw), (1 << rdiv),
  920. *parent_rate, rate);
  921. return rate;
  922. }
  923. static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
  924. unsigned long parent_rate)
  925. {
  926. struct si5351_hw_data *hwdata =
  927. container_of(hw, struct si5351_hw_data, hw);
  928. unsigned long new_rate, new_err, err;
  929. unsigned char rdiv;
  930. /* round to closed rdiv */
  931. rdiv = SI5351_OUTPUT_CLK_DIV_1;
  932. new_rate = parent_rate;
  933. err = abs(new_rate - rate);
  934. do {
  935. new_rate >>= 1;
  936. new_err = abs(new_rate - rate);
  937. if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
  938. break;
  939. rdiv++;
  940. err = new_err;
  941. } while (1);
  942. /* write output divider */
  943. switch (hwdata->num) {
  944. case 6:
  945. si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
  946. SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
  947. break;
  948. case 7:
  949. si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
  950. SI5351_OUTPUT_CLK_DIV_MASK,
  951. rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
  952. break;
  953. default:
  954. si5351_set_bits(hwdata->drvdata,
  955. si5351_msynth_params_address(hwdata->num) + 2,
  956. SI5351_OUTPUT_CLK_DIV_MASK,
  957. rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
  958. }
  959. /* powerup clkout */
  960. si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
  961. SI5351_CLK_POWERDOWN, 0);
  962. dev_dbg(&hwdata->drvdata->client->dev,
  963. "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
  964. __func__, clk_hw_get_name(hw), (1 << rdiv),
  965. parent_rate, rate);
  966. return 0;
  967. }
  968. static const struct clk_ops si5351_clkout_ops = {
  969. .prepare = si5351_clkout_prepare,
  970. .unprepare = si5351_clkout_unprepare,
  971. .set_parent = si5351_clkout_set_parent,
  972. .get_parent = si5351_clkout_get_parent,
  973. .recalc_rate = si5351_clkout_recalc_rate,
  974. .round_rate = si5351_clkout_round_rate,
  975. .set_rate = si5351_clkout_set_rate,
  976. };
  977. /*
  978. * Si5351 i2c probe and DT
  979. */
  980. #ifdef CONFIG_OF
  981. static const struct of_device_id si5351_dt_ids[] = {
  982. { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
  983. { .compatible = "silabs,si5351a-msop",
  984. .data = (void *)SI5351_VARIANT_A3, },
  985. { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
  986. { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
  987. { }
  988. };
  989. MODULE_DEVICE_TABLE(of, si5351_dt_ids);
  990. static int si5351_dt_parse(struct i2c_client *client,
  991. enum si5351_variant variant)
  992. {
  993. struct device_node *child, *np = client->dev.of_node;
  994. struct si5351_platform_data *pdata;
  995. struct property *prop;
  996. const __be32 *p;
  997. int num = 0;
  998. u32 val;
  999. if (np == NULL)
  1000. return 0;
  1001. pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
  1002. if (!pdata)
  1003. return -ENOMEM;
  1004. /*
  1005. * property silabs,pll-source : <num src>, [<..>]
  1006. * allow to selectively set pll source
  1007. */
  1008. of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
  1009. if (num >= 2) {
  1010. dev_err(&client->dev,
  1011. "invalid pll %d on pll-source prop\n", num);
  1012. return -EINVAL;
  1013. }
  1014. p = of_prop_next_u32(prop, p, &val);
  1015. if (!p) {
  1016. dev_err(&client->dev,
  1017. "missing pll-source for pll %d\n", num);
  1018. return -EINVAL;
  1019. }
  1020. switch (val) {
  1021. case 0:
  1022. pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
  1023. break;
  1024. case 1:
  1025. if (variant != SI5351_VARIANT_C) {
  1026. dev_err(&client->dev,
  1027. "invalid parent %d for pll %d\n",
  1028. val, num);
  1029. return -EINVAL;
  1030. }
  1031. pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
  1032. break;
  1033. default:
  1034. dev_err(&client->dev,
  1035. "invalid parent %d for pll %d\n", val, num);
  1036. return -EINVAL;
  1037. }
  1038. }
  1039. /* per clkout properties */
  1040. for_each_child_of_node(np, child) {
  1041. if (of_property_read_u32(child, "reg", &num)) {
  1042. dev_err(&client->dev, "missing reg property of %pOFn\n",
  1043. child);
  1044. goto put_child;
  1045. }
  1046. if (num >= 8 ||
  1047. (variant == SI5351_VARIANT_A3 && num >= 3)) {
  1048. dev_err(&client->dev, "invalid clkout %d\n", num);
  1049. goto put_child;
  1050. }
  1051. if (!of_property_read_u32(child, "silabs,multisynth-source",
  1052. &val)) {
  1053. switch (val) {
  1054. case 0:
  1055. pdata->clkout[num].multisynth_src =
  1056. SI5351_MULTISYNTH_SRC_VCO0;
  1057. break;
  1058. case 1:
  1059. pdata->clkout[num].multisynth_src =
  1060. SI5351_MULTISYNTH_SRC_VCO1;
  1061. break;
  1062. default:
  1063. dev_err(&client->dev,
  1064. "invalid parent %d for multisynth %d\n",
  1065. val, num);
  1066. goto put_child;
  1067. }
  1068. }
  1069. if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
  1070. switch (val) {
  1071. case 0:
  1072. pdata->clkout[num].clkout_src =
  1073. SI5351_CLKOUT_SRC_MSYNTH_N;
  1074. break;
  1075. case 1:
  1076. pdata->clkout[num].clkout_src =
  1077. SI5351_CLKOUT_SRC_MSYNTH_0_4;
  1078. break;
  1079. case 2:
  1080. pdata->clkout[num].clkout_src =
  1081. SI5351_CLKOUT_SRC_XTAL;
  1082. break;
  1083. case 3:
  1084. if (variant != SI5351_VARIANT_C) {
  1085. dev_err(&client->dev,
  1086. "invalid parent %d for clkout %d\n",
  1087. val, num);
  1088. goto put_child;
  1089. }
  1090. pdata->clkout[num].clkout_src =
  1091. SI5351_CLKOUT_SRC_CLKIN;
  1092. break;
  1093. default:
  1094. dev_err(&client->dev,
  1095. "invalid parent %d for clkout %d\n",
  1096. val, num);
  1097. goto put_child;
  1098. }
  1099. }
  1100. if (!of_property_read_u32(child, "silabs,drive-strength",
  1101. &val)) {
  1102. switch (val) {
  1103. case SI5351_DRIVE_2MA:
  1104. case SI5351_DRIVE_4MA:
  1105. case SI5351_DRIVE_6MA:
  1106. case SI5351_DRIVE_8MA:
  1107. pdata->clkout[num].drive = val;
  1108. break;
  1109. default:
  1110. dev_err(&client->dev,
  1111. "invalid drive strength %d for clkout %d\n",
  1112. val, num);
  1113. goto put_child;
  1114. }
  1115. }
  1116. if (!of_property_read_u32(child, "silabs,disable-state",
  1117. &val)) {
  1118. switch (val) {
  1119. case 0:
  1120. pdata->clkout[num].disable_state =
  1121. SI5351_DISABLE_LOW;
  1122. break;
  1123. case 1:
  1124. pdata->clkout[num].disable_state =
  1125. SI5351_DISABLE_HIGH;
  1126. break;
  1127. case 2:
  1128. pdata->clkout[num].disable_state =
  1129. SI5351_DISABLE_FLOATING;
  1130. break;
  1131. case 3:
  1132. pdata->clkout[num].disable_state =
  1133. SI5351_DISABLE_NEVER;
  1134. break;
  1135. default:
  1136. dev_err(&client->dev,
  1137. "invalid disable state %d for clkout %d\n",
  1138. val, num);
  1139. goto put_child;
  1140. }
  1141. }
  1142. if (!of_property_read_u32(child, "clock-frequency", &val))
  1143. pdata->clkout[num].rate = val;
  1144. pdata->clkout[num].pll_master =
  1145. of_property_read_bool(child, "silabs,pll-master");
  1146. pdata->clkout[num].pll_reset =
  1147. of_property_read_bool(child, "silabs,pll-reset");
  1148. }
  1149. client->dev.platform_data = pdata;
  1150. return 0;
  1151. put_child:
  1152. of_node_put(child);
  1153. return -EINVAL;
  1154. }
  1155. static struct clk_hw *
  1156. si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
  1157. {
  1158. struct si5351_driver_data *drvdata = data;
  1159. unsigned int idx = clkspec->args[0];
  1160. if (idx >= drvdata->num_clkout) {
  1161. pr_err("%s: invalid index %u\n", __func__, idx);
  1162. return ERR_PTR(-EINVAL);
  1163. }
  1164. return &drvdata->clkout[idx].hw;
  1165. }
  1166. #else
  1167. static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
  1168. {
  1169. return 0;
  1170. }
  1171. static struct clk_hw *
  1172. si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
  1173. {
  1174. return NULL;
  1175. }
  1176. #endif /* CONFIG_OF */
  1177. static int si5351_i2c_probe(struct i2c_client *client,
  1178. const struct i2c_device_id *id)
  1179. {
  1180. enum si5351_variant variant = (enum si5351_variant)id->driver_data;
  1181. struct si5351_platform_data *pdata;
  1182. struct si5351_driver_data *drvdata;
  1183. struct clk_init_data init;
  1184. const char *parent_names[4];
  1185. u8 num_parents, num_clocks;
  1186. int ret, n;
  1187. ret = si5351_dt_parse(client, variant);
  1188. if (ret)
  1189. return ret;
  1190. pdata = client->dev.platform_data;
  1191. if (!pdata)
  1192. return -EINVAL;
  1193. drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
  1194. if (!drvdata)
  1195. return -ENOMEM;
  1196. i2c_set_clientdata(client, drvdata);
  1197. drvdata->client = client;
  1198. drvdata->variant = variant;
  1199. drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
  1200. drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
  1201. if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
  1202. PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
  1203. return -EPROBE_DEFER;
  1204. /*
  1205. * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
  1206. * VARIANT_C can have CLKIN instead.
  1207. */
  1208. if (IS_ERR(drvdata->pxtal) &&
  1209. (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
  1210. dev_err(&client->dev, "missing parent clock\n");
  1211. return -EINVAL;
  1212. }
  1213. drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
  1214. if (IS_ERR(drvdata->regmap)) {
  1215. dev_err(&client->dev, "failed to allocate register map\n");
  1216. return PTR_ERR(drvdata->regmap);
  1217. }
  1218. /* Disable interrupts */
  1219. si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
  1220. /* Ensure pll select is on XTAL for Si5351A/B */
  1221. if (drvdata->variant != SI5351_VARIANT_C)
  1222. si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
  1223. SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
  1224. /* setup clock configuration */
  1225. for (n = 0; n < 2; n++) {
  1226. ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
  1227. if (ret) {
  1228. dev_err(&client->dev,
  1229. "failed to reparent pll %d to %d\n",
  1230. n, pdata->pll_src[n]);
  1231. return ret;
  1232. }
  1233. }
  1234. for (n = 0; n < 8; n++) {
  1235. ret = _si5351_msynth_reparent(drvdata, n,
  1236. pdata->clkout[n].multisynth_src);
  1237. if (ret) {
  1238. dev_err(&client->dev,
  1239. "failed to reparent multisynth %d to %d\n",
  1240. n, pdata->clkout[n].multisynth_src);
  1241. return ret;
  1242. }
  1243. ret = _si5351_clkout_reparent(drvdata, n,
  1244. pdata->clkout[n].clkout_src);
  1245. if (ret) {
  1246. dev_err(&client->dev,
  1247. "failed to reparent clkout %d to %d\n",
  1248. n, pdata->clkout[n].clkout_src);
  1249. return ret;
  1250. }
  1251. ret = _si5351_clkout_set_drive_strength(drvdata, n,
  1252. pdata->clkout[n].drive);
  1253. if (ret) {
  1254. dev_err(&client->dev,
  1255. "failed set drive strength of clkout%d to %d\n",
  1256. n, pdata->clkout[n].drive);
  1257. return ret;
  1258. }
  1259. ret = _si5351_clkout_set_disable_state(drvdata, n,
  1260. pdata->clkout[n].disable_state);
  1261. if (ret) {
  1262. dev_err(&client->dev,
  1263. "failed set disable state of clkout%d to %d\n",
  1264. n, pdata->clkout[n].disable_state);
  1265. return ret;
  1266. }
  1267. }
  1268. /* register xtal input clock gate */
  1269. memset(&init, 0, sizeof(init));
  1270. init.name = si5351_input_names[0];
  1271. init.ops = &si5351_xtal_ops;
  1272. init.flags = 0;
  1273. if (!IS_ERR(drvdata->pxtal)) {
  1274. drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
  1275. init.parent_names = &drvdata->pxtal_name;
  1276. init.num_parents = 1;
  1277. }
  1278. drvdata->xtal.init = &init;
  1279. ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
  1280. if (ret) {
  1281. dev_err(&client->dev, "unable to register %s\n", init.name);
  1282. return ret;
  1283. }
  1284. /* register clkin input clock gate */
  1285. if (drvdata->variant == SI5351_VARIANT_C) {
  1286. memset(&init, 0, sizeof(init));
  1287. init.name = si5351_input_names[1];
  1288. init.ops = &si5351_clkin_ops;
  1289. if (!IS_ERR(drvdata->pclkin)) {
  1290. drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
  1291. init.parent_names = &drvdata->pclkin_name;
  1292. init.num_parents = 1;
  1293. }
  1294. drvdata->clkin.init = &init;
  1295. ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
  1296. if (ret) {
  1297. dev_err(&client->dev, "unable to register %s\n",
  1298. init.name);
  1299. return ret;
  1300. }
  1301. }
  1302. /* Si5351C allows to mux either xtal or clkin to PLL input */
  1303. num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
  1304. parent_names[0] = si5351_input_names[0];
  1305. parent_names[1] = si5351_input_names[1];
  1306. /* register PLLA */
  1307. drvdata->pll[0].num = 0;
  1308. drvdata->pll[0].drvdata = drvdata;
  1309. drvdata->pll[0].hw.init = &init;
  1310. memset(&init, 0, sizeof(init));
  1311. init.name = si5351_pll_names[0];
  1312. init.ops = &si5351_pll_ops;
  1313. init.flags = 0;
  1314. init.parent_names = parent_names;
  1315. init.num_parents = num_parents;
  1316. ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
  1317. if (ret) {
  1318. dev_err(&client->dev, "unable to register %s\n", init.name);
  1319. return ret;
  1320. }
  1321. /* register PLLB or VXCO (Si5351B) */
  1322. drvdata->pll[1].num = 1;
  1323. drvdata->pll[1].drvdata = drvdata;
  1324. drvdata->pll[1].hw.init = &init;
  1325. memset(&init, 0, sizeof(init));
  1326. if (drvdata->variant == SI5351_VARIANT_B) {
  1327. init.name = si5351_pll_names[2];
  1328. init.ops = &si5351_vxco_ops;
  1329. init.flags = 0;
  1330. init.parent_names = NULL;
  1331. init.num_parents = 0;
  1332. } else {
  1333. init.name = si5351_pll_names[1];
  1334. init.ops = &si5351_pll_ops;
  1335. init.flags = 0;
  1336. init.parent_names = parent_names;
  1337. init.num_parents = num_parents;
  1338. }
  1339. ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
  1340. if (ret) {
  1341. dev_err(&client->dev, "unable to register %s\n", init.name);
  1342. return ret;
  1343. }
  1344. /* register clk multisync and clk out divider */
  1345. num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
  1346. parent_names[0] = si5351_pll_names[0];
  1347. if (drvdata->variant == SI5351_VARIANT_B)
  1348. parent_names[1] = si5351_pll_names[2];
  1349. else
  1350. parent_names[1] = si5351_pll_names[1];
  1351. drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
  1352. sizeof(*drvdata->msynth), GFP_KERNEL);
  1353. drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
  1354. sizeof(*drvdata->clkout), GFP_KERNEL);
  1355. drvdata->num_clkout = num_clocks;
  1356. if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
  1357. ret = -ENOMEM;
  1358. return ret;
  1359. }
  1360. for (n = 0; n < num_clocks; n++) {
  1361. drvdata->msynth[n].num = n;
  1362. drvdata->msynth[n].drvdata = drvdata;
  1363. drvdata->msynth[n].hw.init = &init;
  1364. memset(&init, 0, sizeof(init));
  1365. init.name = si5351_msynth_names[n];
  1366. init.ops = &si5351_msynth_ops;
  1367. init.flags = 0;
  1368. if (pdata->clkout[n].pll_master)
  1369. init.flags |= CLK_SET_RATE_PARENT;
  1370. init.parent_names = parent_names;
  1371. init.num_parents = 2;
  1372. ret = devm_clk_hw_register(&client->dev,
  1373. &drvdata->msynth[n].hw);
  1374. if (ret) {
  1375. dev_err(&client->dev, "unable to register %s\n",
  1376. init.name);
  1377. return ret;
  1378. }
  1379. }
  1380. num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
  1381. parent_names[2] = si5351_input_names[0];
  1382. parent_names[3] = si5351_input_names[1];
  1383. for (n = 0; n < num_clocks; n++) {
  1384. parent_names[0] = si5351_msynth_names[n];
  1385. parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
  1386. si5351_msynth_names[4];
  1387. drvdata->clkout[n].num = n;
  1388. drvdata->clkout[n].drvdata = drvdata;
  1389. drvdata->clkout[n].hw.init = &init;
  1390. memset(&init, 0, sizeof(init));
  1391. init.name = si5351_clkout_names[n];
  1392. init.ops = &si5351_clkout_ops;
  1393. init.flags = 0;
  1394. if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
  1395. init.flags |= CLK_SET_RATE_PARENT;
  1396. init.parent_names = parent_names;
  1397. init.num_parents = num_parents;
  1398. ret = devm_clk_hw_register(&client->dev,
  1399. &drvdata->clkout[n].hw);
  1400. if (ret) {
  1401. dev_err(&client->dev, "unable to register %s\n",
  1402. init.name);
  1403. return ret;
  1404. }
  1405. /* set initial clkout rate */
  1406. if (pdata->clkout[n].rate != 0) {
  1407. int ret;
  1408. ret = clk_set_rate(drvdata->clkout[n].hw.clk,
  1409. pdata->clkout[n].rate);
  1410. if (ret != 0) {
  1411. dev_err(&client->dev, "Cannot set rate : %d\n",
  1412. ret);
  1413. }
  1414. }
  1415. }
  1416. ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get,
  1417. drvdata);
  1418. if (ret) {
  1419. dev_err(&client->dev, "unable to add clk provider\n");
  1420. return ret;
  1421. }
  1422. return 0;
  1423. }
  1424. static int si5351_i2c_remove(struct i2c_client *client)
  1425. {
  1426. of_clk_del_provider(client->dev.of_node);
  1427. return 0;
  1428. }
  1429. static const struct i2c_device_id si5351_i2c_ids[] = {
  1430. { "si5351a", SI5351_VARIANT_A },
  1431. { "si5351a-msop", SI5351_VARIANT_A3 },
  1432. { "si5351b", SI5351_VARIANT_B },
  1433. { "si5351c", SI5351_VARIANT_C },
  1434. { }
  1435. };
  1436. MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
  1437. static struct i2c_driver si5351_driver = {
  1438. .driver = {
  1439. .name = "si5351",
  1440. .of_match_table = of_match_ptr(si5351_dt_ids),
  1441. },
  1442. .probe = si5351_i2c_probe,
  1443. .remove = si5351_i2c_remove,
  1444. .id_table = si5351_i2c_ids,
  1445. };
  1446. module_i2c_driver(si5351_driver);
  1447. MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
  1448. MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
  1449. MODULE_LICENSE("GPL");