clk-si5341.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
  4. * Copyright (C) 2019 Topic Embedded Products
  5. * Author: Mike Looijmans <mike.looijmans@topic.nl>
  6. *
  7. * The Si5341 has 10 outputs and 5 synthesizers.
  8. * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
  9. * The Si5345 is similar to the Si5341, with the addition of fractional input
  10. * dividers and automatic input selection.
  11. * The Si5342 and Si5344 are smaller versions of the Si5345.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/delay.h>
  16. #include <linux/gcd.h>
  17. #include <linux/math64.h>
  18. #include <linux/i2c.h>
  19. #include <linux/module.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include <asm/unaligned.h>
  23. #define SI5341_NUM_INPUTS 4
  24. #define SI5340_MAX_NUM_OUTPUTS 4
  25. #define SI5341_MAX_NUM_OUTPUTS 10
  26. #define SI5342_MAX_NUM_OUTPUTS 2
  27. #define SI5344_MAX_NUM_OUTPUTS 4
  28. #define SI5345_MAX_NUM_OUTPUTS 10
  29. #define SI5340_NUM_SYNTH 4
  30. #define SI5341_NUM_SYNTH 5
  31. #define SI5342_NUM_SYNTH 2
  32. #define SI5344_NUM_SYNTH 4
  33. #define SI5345_NUM_SYNTH 5
  34. /* Range of the synthesizer fractional divider */
  35. #define SI5341_SYNTH_N_MIN 10
  36. #define SI5341_SYNTH_N_MAX 4095
  37. /* The chip can get its input clock from 3 input pins or an XTAL */
  38. /* There is one PLL running at 13500–14256 MHz */
  39. #define SI5341_PLL_VCO_MIN 13500000000ull
  40. #define SI5341_PLL_VCO_MAX 14256000000ull
  41. /* The 5 frequency synthesizers obtain their input from the PLL */
  42. struct clk_si5341_synth {
  43. struct clk_hw hw;
  44. struct clk_si5341 *data;
  45. u8 index;
  46. };
  47. #define to_clk_si5341_synth(_hw) \
  48. container_of(_hw, struct clk_si5341_synth, hw)
  49. /* The output stages can be connected to any synth (full mux) */
  50. struct clk_si5341_output {
  51. struct clk_hw hw;
  52. struct clk_si5341 *data;
  53. u8 index;
  54. };
  55. #define to_clk_si5341_output(_hw) \
  56. container_of(_hw, struct clk_si5341_output, hw)
  57. struct clk_si5341 {
  58. struct clk_hw hw;
  59. struct regmap *regmap;
  60. struct i2c_client *i2c_client;
  61. struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
  62. struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
  63. struct clk *input_clk[SI5341_NUM_INPUTS];
  64. const char *input_clk_name[SI5341_NUM_INPUTS];
  65. const u16 *reg_output_offset;
  66. const u16 *reg_rdiv_offset;
  67. u64 freq_vco; /* 13500–14256 MHz */
  68. u8 num_outputs;
  69. u8 num_synth;
  70. u16 chip_id;
  71. };
  72. #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
  73. struct clk_si5341_output_config {
  74. u8 out_format_drv_bits;
  75. u8 out_cm_ampl_bits;
  76. bool synth_master;
  77. bool always_on;
  78. };
  79. #define SI5341_PAGE 0x0001
  80. #define SI5341_PN_BASE 0x0002
  81. #define SI5341_DEVICE_REV 0x0005
  82. #define SI5341_STATUS 0x000C
  83. #define SI5341_LOS 0x000D
  84. #define SI5341_STATUS_STICKY 0x0011
  85. #define SI5341_LOS_STICKY 0x0012
  86. #define SI5341_SOFT_RST 0x001C
  87. #define SI5341_IN_SEL 0x0021
  88. #define SI5341_DEVICE_READY 0x00FE
  89. #define SI5341_XAXB_CFG 0x090E
  90. #define SI5341_IN_EN 0x0949
  91. #define SI5341_INX_TO_PFD_EN 0x094A
  92. /* Status bits */
  93. #define SI5341_STATUS_SYSINCAL BIT(0)
  94. #define SI5341_STATUS_LOSXAXB BIT(1)
  95. #define SI5341_STATUS_LOSREF BIT(2)
  96. #define SI5341_STATUS_LOL BIT(3)
  97. /* Input selection */
  98. #define SI5341_IN_SEL_MASK 0x06
  99. #define SI5341_IN_SEL_SHIFT 1
  100. #define SI5341_IN_SEL_REGCTRL 0x01
  101. #define SI5341_INX_TO_PFD_SHIFT 4
  102. /* XTAL config bits */
  103. #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
  104. #define SI5341_XAXB_CFG_PDNB BIT(1)
  105. /* Input dividers (48-bit) */
  106. #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
  107. #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
  108. #define SI5341_PX_UPD 0x0230
  109. /* PLL configuration */
  110. #define SI5341_PLL_M_NUM 0x0235
  111. #define SI5341_PLL_M_DEN 0x023B
  112. /* Output configuration */
  113. #define SI5341_OUT_CONFIG(output) \
  114. ((output)->data->reg_output_offset[(output)->index])
  115. #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
  116. #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
  117. #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
  118. #define SI5341_OUT_R_REG(output) \
  119. ((output)->data->reg_rdiv_offset[(output)->index])
  120. /* Synthesize N divider */
  121. #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
  122. #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
  123. #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
  124. /* Synthesizer output enable, phase bypass, power mode */
  125. #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
  126. #define SI5341_SYNTH_N_PIBYP 0x0A04
  127. #define SI5341_SYNTH_N_PDNB 0x0A05
  128. #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
  129. #define SI5341_REGISTER_MAX 0xBFF
  130. /* SI5341_OUT_CONFIG bits */
  131. #define SI5341_OUT_CFG_PDN BIT(0)
  132. #define SI5341_OUT_CFG_OE BIT(1)
  133. #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
  134. /* Static configuration (to be moved to firmware) */
  135. struct si5341_reg_default {
  136. u16 address;
  137. u8 value;
  138. };
  139. static const char * const si5341_input_clock_names[] = {
  140. "in0", "in1", "in2", "xtal"
  141. };
  142. /* Output configuration registers 0..9 are not quite logically organized */
  143. /* Also for si5345 */
  144. static const u16 si5341_reg_output_offset[] = {
  145. 0x0108,
  146. 0x010D,
  147. 0x0112,
  148. 0x0117,
  149. 0x011C,
  150. 0x0121,
  151. 0x0126,
  152. 0x012B,
  153. 0x0130,
  154. 0x013A,
  155. };
  156. /* for si5340, si5342 and si5344 */
  157. static const u16 si5340_reg_output_offset[] = {
  158. 0x0112,
  159. 0x0117,
  160. 0x0126,
  161. 0x012B,
  162. };
  163. /* The location of the R divider registers */
  164. static const u16 si5341_reg_rdiv_offset[] = {
  165. 0x024A,
  166. 0x024D,
  167. 0x0250,
  168. 0x0253,
  169. 0x0256,
  170. 0x0259,
  171. 0x025C,
  172. 0x025F,
  173. 0x0262,
  174. 0x0268,
  175. };
  176. static const u16 si5340_reg_rdiv_offset[] = {
  177. 0x0250,
  178. 0x0253,
  179. 0x025C,
  180. 0x025F,
  181. };
  182. /*
  183. * Programming sequence from ClockBuilder, settings to initialize the system
  184. * using only the XTAL input, without pre-divider.
  185. * This also contains settings that aren't mentioned anywhere in the datasheet.
  186. * The "known" settings like synth and output configuration are done later.
  187. */
  188. static const struct si5341_reg_default si5341_reg_defaults[] = {
  189. { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
  190. { 0x0018, 0xFF }, /* INT mask */
  191. { 0x0021, 0x0F }, /* Select XTAL as input */
  192. { 0x0022, 0x00 }, /* Not in datasheet */
  193. { 0x002B, 0x02 }, /* SPI config */
  194. { 0x002C, 0x20 }, /* LOS enable for XTAL */
  195. { 0x002D, 0x00 }, /* LOS timing */
  196. { 0x002E, 0x00 },
  197. { 0x002F, 0x00 },
  198. { 0x0030, 0x00 },
  199. { 0x0031, 0x00 },
  200. { 0x0032, 0x00 },
  201. { 0x0033, 0x00 },
  202. { 0x0034, 0x00 },
  203. { 0x0035, 0x00 },
  204. { 0x0036, 0x00 },
  205. { 0x0037, 0x00 },
  206. { 0x0038, 0x00 }, /* LOS setting (thresholds) */
  207. { 0x0039, 0x00 },
  208. { 0x003A, 0x00 },
  209. { 0x003B, 0x00 },
  210. { 0x003C, 0x00 },
  211. { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
  212. { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
  213. { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
  214. { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
  215. { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
  216. { 0x009E, 0x00 }, /* Not in datasheet */
  217. { 0x0102, 0x01 }, /* Enable outputs */
  218. { 0x013F, 0x00 }, /* Not in datasheet */
  219. { 0x0140, 0x00 }, /* Not in datasheet */
  220. { 0x0141, 0x40 }, /* OUT LOS */
  221. { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
  222. { 0x0203, 0x00 },
  223. { 0x0204, 0x00 },
  224. { 0x0205, 0x00 },
  225. { 0x0206, 0x00 }, /* PXAXB (2^x) */
  226. { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
  227. { 0x0209, 0x00 },
  228. { 0x020A, 0x00 },
  229. { 0x020B, 0x00 },
  230. { 0x020C, 0x00 },
  231. { 0x020D, 0x00 },
  232. { 0x020E, 0x00 },
  233. { 0x020F, 0x00 },
  234. { 0x0210, 0x00 },
  235. { 0x0211, 0x00 },
  236. { 0x0212, 0x00 },
  237. { 0x0213, 0x00 },
  238. { 0x0214, 0x00 },
  239. { 0x0215, 0x00 },
  240. { 0x0216, 0x00 },
  241. { 0x0217, 0x00 },
  242. { 0x0218, 0x00 },
  243. { 0x0219, 0x00 },
  244. { 0x021A, 0x00 },
  245. { 0x021B, 0x00 },
  246. { 0x021C, 0x00 },
  247. { 0x021D, 0x00 },
  248. { 0x021E, 0x00 },
  249. { 0x021F, 0x00 },
  250. { 0x0220, 0x00 },
  251. { 0x0221, 0x00 },
  252. { 0x0222, 0x00 },
  253. { 0x0223, 0x00 },
  254. { 0x0224, 0x00 },
  255. { 0x0225, 0x00 },
  256. { 0x0226, 0x00 },
  257. { 0x0227, 0x00 },
  258. { 0x0228, 0x00 },
  259. { 0x0229, 0x00 },
  260. { 0x022A, 0x00 },
  261. { 0x022B, 0x00 },
  262. { 0x022C, 0x00 },
  263. { 0x022D, 0x00 },
  264. { 0x022E, 0x00 },
  265. { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
  266. { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
  267. { 0x026C, 0x00 },
  268. { 0x026D, 0x00 },
  269. { 0x026E, 0x00 },
  270. { 0x026F, 0x00 },
  271. { 0x0270, 0x00 },
  272. { 0x0271, 0x00 },
  273. { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
  274. { 0x0339, 0x1F }, /* N_FSTEP_MSK */
  275. { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
  276. { 0x033C, 0x00 },
  277. { 0x033D, 0x00 },
  278. { 0x033E, 0x00 },
  279. { 0x033F, 0x00 },
  280. { 0x0340, 0x00 },
  281. { 0x0341, 0x00 },
  282. { 0x0342, 0x00 },
  283. { 0x0343, 0x00 },
  284. { 0x0344, 0x00 },
  285. { 0x0345, 0x00 },
  286. { 0x0346, 0x00 },
  287. { 0x0347, 0x00 },
  288. { 0x0348, 0x00 },
  289. { 0x0349, 0x00 },
  290. { 0x034A, 0x00 },
  291. { 0x034B, 0x00 },
  292. { 0x034C, 0x00 },
  293. { 0x034D, 0x00 },
  294. { 0x034E, 0x00 },
  295. { 0x034F, 0x00 },
  296. { 0x0350, 0x00 },
  297. { 0x0351, 0x00 },
  298. { 0x0352, 0x00 },
  299. { 0x0353, 0x00 },
  300. { 0x0354, 0x00 },
  301. { 0x0355, 0x00 },
  302. { 0x0356, 0x00 },
  303. { 0x0357, 0x00 },
  304. { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
  305. { 0x0359, 0x00 }, /* Nx_DELAY */
  306. { 0x035A, 0x00 },
  307. { 0x035B, 0x00 },
  308. { 0x035C, 0x00 },
  309. { 0x035D, 0x00 },
  310. { 0x035E, 0x00 },
  311. { 0x035F, 0x00 },
  312. { 0x0360, 0x00 },
  313. { 0x0361, 0x00 },
  314. { 0x0362, 0x00 }, /* Nx_DELAY end */
  315. { 0x0802, 0x00 }, /* Not in datasheet */
  316. { 0x0803, 0x00 }, /* Not in datasheet */
  317. { 0x0804, 0x00 }, /* Not in datasheet */
  318. { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
  319. { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
  320. { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
  321. { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
  322. { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
  323. { 0x0A02, 0x00 }, /* Not in datasheet */
  324. { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
  325. { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
  326. { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
  327. };
  328. /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
  329. static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
  330. u64 *val1, u32 *val2)
  331. {
  332. int err;
  333. u8 r[10];
  334. err = regmap_bulk_read(regmap, reg, r, 10);
  335. if (err < 0)
  336. return err;
  337. *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
  338. (get_unaligned_le32(r));
  339. *val2 = get_unaligned_le32(&r[6]);
  340. return 0;
  341. }
  342. static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
  343. u64 n_num, u32 n_den)
  344. {
  345. u8 r[10];
  346. /* Shift left as far as possible without overflowing */
  347. while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
  348. n_num <<= 1;
  349. n_den <<= 1;
  350. }
  351. /* 44 bits (6 bytes) numerator */
  352. put_unaligned_le32(n_num, r);
  353. r[4] = (n_num >> 32) & 0xff;
  354. r[5] = (n_num >> 40) & 0x0f;
  355. /* 32 bits denominator */
  356. put_unaligned_le32(n_den, &r[6]);
  357. /* Program the fraction */
  358. return regmap_bulk_write(regmap, reg, r, sizeof(r));
  359. }
  360. /* VCO, we assume it runs at a constant frequency */
  361. static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
  362. unsigned long parent_rate)
  363. {
  364. struct clk_si5341 *data = to_clk_si5341(hw);
  365. int err;
  366. u64 res;
  367. u64 m_num;
  368. u32 m_den;
  369. unsigned int shift;
  370. /* Assume that PDIV is not being used, just read the PLL setting */
  371. err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
  372. &m_num, &m_den);
  373. if (err < 0)
  374. return 0;
  375. if (!m_num || !m_den)
  376. return 0;
  377. /*
  378. * Though m_num is 64-bit, only the upper bits are actually used. While
  379. * calculating m_num and m_den, they are shifted as far as possible to
  380. * the left. To avoid 96-bit division here, we just shift them back so
  381. * we can do with just 64 bits.
  382. */
  383. shift = 0;
  384. res = m_num;
  385. while (res & 0xffff00000000ULL) {
  386. ++shift;
  387. res >>= 1;
  388. }
  389. res *= parent_rate;
  390. do_div(res, (m_den >> shift));
  391. /* We cannot return the actual frequency in 32 bit, store it locally */
  392. data->freq_vco = res;
  393. /* Report kHz since the value is out of range */
  394. do_div(res, 1000);
  395. return (unsigned long)res;
  396. }
  397. static int si5341_clk_get_selected_input(struct clk_si5341 *data)
  398. {
  399. int err;
  400. u32 val;
  401. err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
  402. if (err < 0)
  403. return err;
  404. return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
  405. }
  406. static u8 si5341_clk_get_parent(struct clk_hw *hw)
  407. {
  408. struct clk_si5341 *data = to_clk_si5341(hw);
  409. int res = si5341_clk_get_selected_input(data);
  410. if (res < 0)
  411. return 0; /* Apparently we cannot report errors */
  412. return res;
  413. }
  414. static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
  415. {
  416. int err;
  417. u8 val;
  418. val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
  419. /* Enable register-based input selection */
  420. val |= SI5341_IN_SEL_REGCTRL;
  421. err = regmap_update_bits(data->regmap,
  422. SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
  423. if (err < 0)
  424. return err;
  425. if (index < 3) {
  426. /* Enable input buffer for selected input */
  427. err = regmap_update_bits(data->regmap,
  428. SI5341_IN_EN, 0x07, BIT(index));
  429. if (err < 0)
  430. return err;
  431. /* Enables the input to phase detector */
  432. err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
  433. 0x7 << SI5341_INX_TO_PFD_SHIFT,
  434. BIT(index + SI5341_INX_TO_PFD_SHIFT));
  435. if (err < 0)
  436. return err;
  437. /* Power down XTAL oscillator and buffer */
  438. err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
  439. SI5341_XAXB_CFG_PDNB, 0);
  440. if (err < 0)
  441. return err;
  442. /*
  443. * Set the P divider to "1". There's no explanation in the
  444. * datasheet of these registers, but the clockbuilder software
  445. * programs a "1" when the input is being used.
  446. */
  447. err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
  448. if (err < 0)
  449. return err;
  450. err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
  451. if (err < 0)
  452. return err;
  453. /* Set update PDIV bit */
  454. err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
  455. if (err < 0)
  456. return err;
  457. } else {
  458. /* Disable all input buffers */
  459. err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
  460. if (err < 0)
  461. return err;
  462. /* Disable input to phase detector */
  463. err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
  464. 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
  465. if (err < 0)
  466. return err;
  467. /* Power up XTAL oscillator and buffer */
  468. err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
  469. SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
  470. if (err < 0)
  471. return err;
  472. }
  473. return 0;
  474. }
  475. static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
  476. {
  477. struct clk_si5341 *data = to_clk_si5341(hw);
  478. return si5341_clk_reparent(data, index);
  479. }
  480. static const struct clk_ops si5341_clk_ops = {
  481. .set_parent = si5341_clk_set_parent,
  482. .get_parent = si5341_clk_get_parent,
  483. .recalc_rate = si5341_clk_recalc_rate,
  484. };
  485. /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
  486. /* The synthesizer is on if all power and enable bits are set */
  487. static int si5341_synth_clk_is_on(struct clk_hw *hw)
  488. {
  489. struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
  490. int err;
  491. u32 val;
  492. u8 index = synth->index;
  493. err = regmap_read(synth->data->regmap,
  494. SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
  495. if (err < 0)
  496. return 0;
  497. if (!(val & BIT(index)))
  498. return 0;
  499. err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
  500. if (err < 0)
  501. return 0;
  502. if (!(val & BIT(index)))
  503. return 0;
  504. /* This bit must be 0 for the synthesizer to receive clock input */
  505. err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
  506. if (err < 0)
  507. return 0;
  508. return !(val & BIT(index));
  509. }
  510. static void si5341_synth_clk_unprepare(struct clk_hw *hw)
  511. {
  512. struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
  513. u8 index = synth->index; /* In range 0..5 */
  514. u8 mask = BIT(index);
  515. /* Disable output */
  516. regmap_update_bits(synth->data->regmap,
  517. SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
  518. /* Power down */
  519. regmap_update_bits(synth->data->regmap,
  520. SI5341_SYNTH_N_PDNB, mask, 0);
  521. /* Disable clock input to synth (set to 1 to disable) */
  522. regmap_update_bits(synth->data->regmap,
  523. SI5341_SYNTH_N_CLK_DIS, mask, mask);
  524. }
  525. static int si5341_synth_clk_prepare(struct clk_hw *hw)
  526. {
  527. struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
  528. int err;
  529. u8 index = synth->index;
  530. u8 mask = BIT(index);
  531. /* Power up */
  532. err = regmap_update_bits(synth->data->regmap,
  533. SI5341_SYNTH_N_PDNB, mask, mask);
  534. if (err < 0)
  535. return err;
  536. /* Enable clock input to synth (set bit to 0 to enable) */
  537. err = regmap_update_bits(synth->data->regmap,
  538. SI5341_SYNTH_N_CLK_DIS, mask, 0);
  539. if (err < 0)
  540. return err;
  541. /* Enable output */
  542. return regmap_update_bits(synth->data->regmap,
  543. SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
  544. }
  545. /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
  546. static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
  547. unsigned long parent_rate)
  548. {
  549. struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
  550. u64 f;
  551. u64 n_num;
  552. u32 n_den;
  553. int err;
  554. err = si5341_decode_44_32(synth->data->regmap,
  555. SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
  556. if (err < 0)
  557. return err;
  558. /* Check for bogus/uninitialized settings */
  559. if (!n_num || !n_den)
  560. return 0;
  561. /*
  562. * n_num and n_den are shifted left as much as possible, so to prevent
  563. * overflow in 64-bit math, we shift n_den 4 bits to the right
  564. */
  565. f = synth->data->freq_vco;
  566. f *= n_den >> 4;
  567. /* Now we need to to 64-bit division: f/n_num */
  568. /* And compensate for the 4 bits we dropped */
  569. f = div64_u64(f, (n_num >> 4));
  570. return f;
  571. }
  572. static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  573. unsigned long *parent_rate)
  574. {
  575. struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
  576. u64 f;
  577. /* The synthesizer accuracy is such that anything in range will work */
  578. f = synth->data->freq_vco;
  579. do_div(f, SI5341_SYNTH_N_MAX);
  580. if (rate < f)
  581. return f;
  582. f = synth->data->freq_vco;
  583. do_div(f, SI5341_SYNTH_N_MIN);
  584. if (rate > f)
  585. return f;
  586. return rate;
  587. }
  588. static int si5341_synth_program(struct clk_si5341_synth *synth,
  589. u64 n_num, u32 n_den, bool is_integer)
  590. {
  591. int err;
  592. u8 index = synth->index;
  593. err = si5341_encode_44_32(synth->data->regmap,
  594. SI5341_SYNTH_N_NUM(index), n_num, n_den);
  595. err = regmap_update_bits(synth->data->regmap,
  596. SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
  597. if (err < 0)
  598. return err;
  599. return regmap_write(synth->data->regmap,
  600. SI5341_SYNTH_N_UPD(index), 0x01);
  601. }
  602. static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  603. unsigned long parent_rate)
  604. {
  605. struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
  606. u64 n_num;
  607. u32 n_den;
  608. u32 r;
  609. u32 g;
  610. bool is_integer;
  611. n_num = synth->data->freq_vco;
  612. /* see if there's an integer solution */
  613. r = do_div(n_num, rate);
  614. is_integer = (r == 0);
  615. if (is_integer) {
  616. /* Integer divider equal to n_num */
  617. n_den = 1;
  618. } else {
  619. /* Calculate a fractional solution */
  620. g = gcd(r, rate);
  621. n_den = rate / g;
  622. n_num *= n_den;
  623. n_num += r / g;
  624. }
  625. dev_dbg(&synth->data->i2c_client->dev,
  626. "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
  627. synth->index, n_num, n_den,
  628. is_integer ? "int" : "frac");
  629. return si5341_synth_program(synth, n_num, n_den, is_integer);
  630. }
  631. static const struct clk_ops si5341_synth_clk_ops = {
  632. .is_prepared = si5341_synth_clk_is_on,
  633. .prepare = si5341_synth_clk_prepare,
  634. .unprepare = si5341_synth_clk_unprepare,
  635. .recalc_rate = si5341_synth_clk_recalc_rate,
  636. .round_rate = si5341_synth_clk_round_rate,
  637. .set_rate = si5341_synth_clk_set_rate,
  638. };
  639. static int si5341_output_clk_is_on(struct clk_hw *hw)
  640. {
  641. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  642. int err;
  643. u32 val;
  644. err = regmap_read(output->data->regmap,
  645. SI5341_OUT_CONFIG(output), &val);
  646. if (err < 0)
  647. return err;
  648. /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
  649. return (val & 0x03) == SI5341_OUT_CFG_OE;
  650. }
  651. /* Disables and then powers down the output */
  652. static void si5341_output_clk_unprepare(struct clk_hw *hw)
  653. {
  654. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  655. regmap_update_bits(output->data->regmap,
  656. SI5341_OUT_CONFIG(output),
  657. SI5341_OUT_CFG_OE, 0);
  658. regmap_update_bits(output->data->regmap,
  659. SI5341_OUT_CONFIG(output),
  660. SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
  661. }
  662. /* Powers up and then enables the output */
  663. static int si5341_output_clk_prepare(struct clk_hw *hw)
  664. {
  665. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  666. int err;
  667. err = regmap_update_bits(output->data->regmap,
  668. SI5341_OUT_CONFIG(output),
  669. SI5341_OUT_CFG_PDN, 0);
  670. if (err < 0)
  671. return err;
  672. return regmap_update_bits(output->data->regmap,
  673. SI5341_OUT_CONFIG(output),
  674. SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
  675. }
  676. static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
  677. unsigned long parent_rate)
  678. {
  679. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  680. int err;
  681. u32 val;
  682. u32 r_divider;
  683. u8 r[3];
  684. err = regmap_read(output->data->regmap,
  685. SI5341_OUT_CONFIG(output), &val);
  686. if (err < 0)
  687. return err;
  688. /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
  689. if (val & SI5341_OUT_CFG_RDIV_FORCE2)
  690. return parent_rate / 2;
  691. err = regmap_bulk_read(output->data->regmap,
  692. SI5341_OUT_R_REG(output), r, 3);
  693. if (err < 0)
  694. return err;
  695. /* Calculate value as 24-bit integer*/
  696. r_divider = r[2] << 16 | r[1] << 8 | r[0];
  697. /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
  698. if (!r_divider)
  699. return 0;
  700. /* Divider is 2*(Rx_REG+1) */
  701. r_divider += 1;
  702. r_divider <<= 1;
  703. return parent_rate / r_divider;
  704. }
  705. static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  706. unsigned long *parent_rate)
  707. {
  708. unsigned long r;
  709. if (!rate)
  710. return 0;
  711. r = *parent_rate >> 1;
  712. /* If rate is an even divisor, no changes to parent required */
  713. if (r && !(r % rate))
  714. return (long)rate;
  715. if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  716. if (rate > 200000000) {
  717. /* minimum r-divider is 2 */
  718. r = 2;
  719. } else {
  720. /* Take a parent frequency near 400 MHz */
  721. r = (400000000u / rate) & ~1;
  722. }
  723. *parent_rate = r * rate;
  724. } else {
  725. /* We cannot change our parent's rate, report what we can do */
  726. r /= rate;
  727. rate = *parent_rate / (r << 1);
  728. }
  729. return rate;
  730. }
  731. static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  732. unsigned long parent_rate)
  733. {
  734. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  735. u32 r_div;
  736. int err;
  737. u8 r[3];
  738. if (!rate)
  739. return -EINVAL;
  740. /* Frequency divider is (r_div + 1) * 2 */
  741. r_div = (parent_rate / rate) >> 1;
  742. if (r_div <= 1)
  743. r_div = 0;
  744. else if (r_div >= BIT(24))
  745. r_div = BIT(24) - 1;
  746. else
  747. --r_div;
  748. /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
  749. err = regmap_update_bits(output->data->regmap,
  750. SI5341_OUT_CONFIG(output),
  751. SI5341_OUT_CFG_RDIV_FORCE2,
  752. (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
  753. if (err < 0)
  754. return err;
  755. /* Always write Rx_REG, because a zero value disables the divider */
  756. r[0] = r_div ? (r_div & 0xff) : 1;
  757. r[1] = (r_div >> 8) & 0xff;
  758. r[2] = (r_div >> 16) & 0xff;
  759. err = regmap_bulk_write(output->data->regmap,
  760. SI5341_OUT_R_REG(output), r, 3);
  761. return 0;
  762. }
  763. static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
  764. {
  765. return regmap_update_bits(output->data->regmap,
  766. SI5341_OUT_MUX_SEL(output), 0x07, index);
  767. }
  768. static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
  769. {
  770. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  771. if (index >= output->data->num_synth)
  772. return -EINVAL;
  773. return si5341_output_reparent(output, index);
  774. }
  775. static u8 si5341_output_get_parent(struct clk_hw *hw)
  776. {
  777. struct clk_si5341_output *output = to_clk_si5341_output(hw);
  778. u32 val;
  779. regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
  780. return val & 0x7;
  781. }
  782. static const struct clk_ops si5341_output_clk_ops = {
  783. .is_prepared = si5341_output_clk_is_on,
  784. .prepare = si5341_output_clk_prepare,
  785. .unprepare = si5341_output_clk_unprepare,
  786. .recalc_rate = si5341_output_clk_recalc_rate,
  787. .round_rate = si5341_output_clk_round_rate,
  788. .set_rate = si5341_output_clk_set_rate,
  789. .set_parent = si5341_output_set_parent,
  790. .get_parent = si5341_output_get_parent,
  791. };
  792. /*
  793. * The chip can be bought in a pre-programmed version, or one can program the
  794. * NVM in the chip to boot up in a preset mode. This routine tries to determine
  795. * if that's the case, or if we need to reset and program everything from
  796. * scratch. Returns negative error, or true/false.
  797. */
  798. static int si5341_is_programmed_already(struct clk_si5341 *data)
  799. {
  800. int err;
  801. u8 r[4];
  802. /* Read the PLL divider value, it must have a non-zero value */
  803. err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
  804. r, ARRAY_SIZE(r));
  805. if (err < 0)
  806. return err;
  807. return !!get_unaligned_le32(r);
  808. }
  809. static struct clk_hw *
  810. of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
  811. {
  812. struct clk_si5341 *data = _data;
  813. unsigned int idx = clkspec->args[1];
  814. unsigned int group = clkspec->args[0];
  815. switch (group) {
  816. case 0:
  817. if (idx >= data->num_outputs) {
  818. dev_err(&data->i2c_client->dev,
  819. "invalid output index %u\n", idx);
  820. return ERR_PTR(-EINVAL);
  821. }
  822. return &data->clk[idx].hw;
  823. case 1:
  824. if (idx >= data->num_synth) {
  825. dev_err(&data->i2c_client->dev,
  826. "invalid synthesizer index %u\n", idx);
  827. return ERR_PTR(-EINVAL);
  828. }
  829. return &data->synth[idx].hw;
  830. case 2:
  831. if (idx > 0) {
  832. dev_err(&data->i2c_client->dev,
  833. "invalid PLL index %u\n", idx);
  834. return ERR_PTR(-EINVAL);
  835. }
  836. return &data->hw;
  837. default:
  838. dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
  839. return ERR_PTR(-EINVAL);
  840. }
  841. }
  842. static int si5341_probe_chip_id(struct clk_si5341 *data)
  843. {
  844. int err;
  845. u8 reg[4];
  846. u16 model;
  847. err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
  848. ARRAY_SIZE(reg));
  849. if (err < 0) {
  850. dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
  851. return err;
  852. }
  853. model = get_unaligned_le16(reg);
  854. dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
  855. model, reg[2], reg[3]);
  856. switch (model) {
  857. case 0x5340:
  858. data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
  859. data->num_synth = SI5340_NUM_SYNTH;
  860. data->reg_output_offset = si5340_reg_output_offset;
  861. data->reg_rdiv_offset = si5340_reg_rdiv_offset;
  862. break;
  863. case 0x5341:
  864. data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
  865. data->num_synth = SI5341_NUM_SYNTH;
  866. data->reg_output_offset = si5341_reg_output_offset;
  867. data->reg_rdiv_offset = si5341_reg_rdiv_offset;
  868. break;
  869. case 0x5342:
  870. data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
  871. data->num_synth = SI5342_NUM_SYNTH;
  872. data->reg_output_offset = si5340_reg_output_offset;
  873. data->reg_rdiv_offset = si5340_reg_rdiv_offset;
  874. break;
  875. case 0x5344:
  876. data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
  877. data->num_synth = SI5344_NUM_SYNTH;
  878. data->reg_output_offset = si5340_reg_output_offset;
  879. data->reg_rdiv_offset = si5340_reg_rdiv_offset;
  880. break;
  881. case 0x5345:
  882. data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
  883. data->num_synth = SI5345_NUM_SYNTH;
  884. data->reg_output_offset = si5341_reg_output_offset;
  885. data->reg_rdiv_offset = si5341_reg_rdiv_offset;
  886. break;
  887. default:
  888. dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
  889. model);
  890. return -EINVAL;
  891. }
  892. data->chip_id = model;
  893. return 0;
  894. }
  895. /* Read active settings into the regmap cache for later reference */
  896. static int si5341_read_settings(struct clk_si5341 *data)
  897. {
  898. int err;
  899. u8 i;
  900. u8 r[10];
  901. err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
  902. if (err < 0)
  903. return err;
  904. err = regmap_bulk_read(data->regmap,
  905. SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
  906. if (err < 0)
  907. return err;
  908. err = regmap_bulk_read(data->regmap,
  909. SI5341_SYNTH_N_CLK_DIS, r, 1);
  910. if (err < 0)
  911. return err;
  912. for (i = 0; i < data->num_synth; ++i) {
  913. err = regmap_bulk_read(data->regmap,
  914. SI5341_SYNTH_N_NUM(i), r, 10);
  915. if (err < 0)
  916. return err;
  917. }
  918. for (i = 0; i < data->num_outputs; ++i) {
  919. err = regmap_bulk_read(data->regmap,
  920. data->reg_output_offset[i], r, 4);
  921. if (err < 0)
  922. return err;
  923. err = regmap_bulk_read(data->regmap,
  924. data->reg_rdiv_offset[i], r, 3);
  925. if (err < 0)
  926. return err;
  927. }
  928. return 0;
  929. }
  930. static int si5341_write_multiple(struct clk_si5341 *data,
  931. const struct si5341_reg_default *values, unsigned int num_values)
  932. {
  933. unsigned int i;
  934. int res;
  935. for (i = 0; i < num_values; ++i) {
  936. res = regmap_write(data->regmap,
  937. values[i].address, values[i].value);
  938. if (res < 0) {
  939. dev_err(&data->i2c_client->dev,
  940. "Failed to write %#x:%#x\n",
  941. values[i].address, values[i].value);
  942. return res;
  943. }
  944. }
  945. return 0;
  946. }
  947. static const struct si5341_reg_default si5341_preamble[] = {
  948. { 0x0B25, 0x00 },
  949. { 0x0502, 0x01 },
  950. { 0x0505, 0x03 },
  951. { 0x0957, 0x17 },
  952. { 0x0B4E, 0x1A },
  953. };
  954. static const struct si5341_reg_default si5345_preamble[] = {
  955. { 0x0B25, 0x00 },
  956. { 0x0540, 0x01 },
  957. };
  958. static int si5341_send_preamble(struct clk_si5341 *data)
  959. {
  960. int res;
  961. u32 revision;
  962. /* For revision 2 and up, the values are slightly different */
  963. res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
  964. if (res < 0)
  965. return res;
  966. /* Write "preamble" as specified by datasheet */
  967. res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
  968. if (res < 0)
  969. return res;
  970. /* The si5342..si5345 require a different preamble */
  971. if (data->chip_id > 0x5341)
  972. res = si5341_write_multiple(data,
  973. si5345_preamble, ARRAY_SIZE(si5345_preamble));
  974. else
  975. res = si5341_write_multiple(data,
  976. si5341_preamble, ARRAY_SIZE(si5341_preamble));
  977. if (res < 0)
  978. return res;
  979. /* Datasheet specifies a 300ms wait after sending the preamble */
  980. msleep(300);
  981. return 0;
  982. }
  983. /* Perform a soft reset and write post-amble */
  984. static int si5341_finalize_defaults(struct clk_si5341 *data)
  985. {
  986. int res;
  987. u32 revision;
  988. res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
  989. if (res < 0)
  990. return res;
  991. dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
  992. res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
  993. if (res < 0)
  994. return res;
  995. /* The si5342..si5345 have an additional post-amble */
  996. if (data->chip_id > 0x5341) {
  997. res = regmap_write(data->regmap, 0x540, 0x0);
  998. if (res < 0)
  999. return res;
  1000. }
  1001. /* Datasheet does not explain these nameless registers */
  1002. res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
  1003. if (res < 0)
  1004. return res;
  1005. res = regmap_write(data->regmap, 0x0B25, 0x02);
  1006. if (res < 0)
  1007. return res;
  1008. return 0;
  1009. }
  1010. static const struct regmap_range si5341_regmap_volatile_range[] = {
  1011. regmap_reg_range(0x000C, 0x0012), /* Status */
  1012. regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
  1013. regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
  1014. /* Update bits for P divider and synth config */
  1015. regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
  1016. regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
  1017. regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
  1018. regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
  1019. regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
  1020. regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
  1021. };
  1022. static const struct regmap_access_table si5341_regmap_volatile = {
  1023. .yes_ranges = si5341_regmap_volatile_range,
  1024. .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
  1025. };
  1026. /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
  1027. static const struct regmap_range_cfg si5341_regmap_ranges[] = {
  1028. {
  1029. .range_min = 0,
  1030. .range_max = SI5341_REGISTER_MAX,
  1031. .selector_reg = SI5341_PAGE,
  1032. .selector_mask = 0xff,
  1033. .selector_shift = 0,
  1034. .window_start = 0,
  1035. .window_len = 256,
  1036. },
  1037. };
  1038. static int si5341_wait_device_ready(struct i2c_client *client)
  1039. {
  1040. int count;
  1041. /* Datasheet warns: Any attempt to read or write any register other
  1042. * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
  1043. * NVM programming and may corrupt the register contents, as they are
  1044. * read from NVM. Note that this includes accesses to the PAGE register.
  1045. * Also: DEVICE_READY is available on every register page, so no page
  1046. * change is needed to read it.
  1047. * Do this outside regmap to avoid automatic PAGE register access.
  1048. * May take up to 300ms to complete.
  1049. */
  1050. for (count = 0; count < 15; ++count) {
  1051. s32 result = i2c_smbus_read_byte_data(client,
  1052. SI5341_DEVICE_READY);
  1053. if (result < 0)
  1054. return result;
  1055. if (result == 0x0F)
  1056. return 0;
  1057. msleep(20);
  1058. }
  1059. dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
  1060. return -EIO;
  1061. }
  1062. static const struct regmap_config si5341_regmap_config = {
  1063. .reg_bits = 8,
  1064. .val_bits = 8,
  1065. .cache_type = REGCACHE_RBTREE,
  1066. .ranges = si5341_regmap_ranges,
  1067. .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
  1068. .max_register = SI5341_REGISTER_MAX,
  1069. .volatile_table = &si5341_regmap_volatile,
  1070. };
  1071. static int si5341_dt_parse_dt(struct i2c_client *client,
  1072. struct clk_si5341_output_config *config)
  1073. {
  1074. struct device_node *child;
  1075. struct device_node *np = client->dev.of_node;
  1076. u32 num;
  1077. u32 val;
  1078. memset(config, 0, sizeof(struct clk_si5341_output_config) *
  1079. SI5341_MAX_NUM_OUTPUTS);
  1080. for_each_child_of_node(np, child) {
  1081. if (of_property_read_u32(child, "reg", &num)) {
  1082. dev_err(&client->dev, "missing reg property of %s\n",
  1083. child->name);
  1084. goto put_child;
  1085. }
  1086. if (num >= SI5341_MAX_NUM_OUTPUTS) {
  1087. dev_err(&client->dev, "invalid clkout %d\n", num);
  1088. goto put_child;
  1089. }
  1090. if (!of_property_read_u32(child, "silabs,format", &val)) {
  1091. /* Set cm and ampl conservatively to 3v3 settings */
  1092. switch (val) {
  1093. case 1: /* normal differential */
  1094. config[num].out_cm_ampl_bits = 0x33;
  1095. break;
  1096. case 2: /* low-power differential */
  1097. config[num].out_cm_ampl_bits = 0x13;
  1098. break;
  1099. case 4: /* LVCMOS */
  1100. config[num].out_cm_ampl_bits = 0x33;
  1101. /* Set SI recommended impedance for LVCMOS */
  1102. config[num].out_format_drv_bits |= 0xc0;
  1103. break;
  1104. default:
  1105. dev_err(&client->dev,
  1106. "invalid silabs,format %u for %u\n",
  1107. val, num);
  1108. goto put_child;
  1109. }
  1110. config[num].out_format_drv_bits &= ~0x07;
  1111. config[num].out_format_drv_bits |= val & 0x07;
  1112. /* Always enable the SYNC feature */
  1113. config[num].out_format_drv_bits |= 0x08;
  1114. }
  1115. if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
  1116. if (val > 0xf) {
  1117. dev_err(&client->dev,
  1118. "invalid silabs,common-mode %u\n",
  1119. val);
  1120. goto put_child;
  1121. }
  1122. config[num].out_cm_ampl_bits &= 0xf0;
  1123. config[num].out_cm_ampl_bits |= val & 0x0f;
  1124. }
  1125. if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
  1126. if (val > 0xf) {
  1127. dev_err(&client->dev,
  1128. "invalid silabs,amplitude %u\n",
  1129. val);
  1130. goto put_child;
  1131. }
  1132. config[num].out_cm_ampl_bits &= 0x0f;
  1133. config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
  1134. }
  1135. if (of_property_read_bool(child, "silabs,disable-high"))
  1136. config[num].out_format_drv_bits |= 0x10;
  1137. config[num].synth_master =
  1138. of_property_read_bool(child, "silabs,synth-master");
  1139. config[num].always_on =
  1140. of_property_read_bool(child, "always-on");
  1141. }
  1142. return 0;
  1143. put_child:
  1144. of_node_put(child);
  1145. return -EINVAL;
  1146. }
  1147. /*
  1148. * If not pre-configured, calculate and set the PLL configuration manually.
  1149. * For low-jitter performance, the PLL should be set such that the synthesizers
  1150. * only need integer division.
  1151. * Without any user guidance, we'll set the PLL to 14GHz, which still allows
  1152. * the chip to generate any frequency on its outputs, but jitter performance
  1153. * may be sub-optimal.
  1154. */
  1155. static int si5341_initialize_pll(struct clk_si5341 *data)
  1156. {
  1157. struct device_node *np = data->i2c_client->dev.of_node;
  1158. u32 m_num = 0;
  1159. u32 m_den = 0;
  1160. int sel;
  1161. if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
  1162. dev_err(&data->i2c_client->dev,
  1163. "PLL configuration requires silabs,pll-m-num\n");
  1164. }
  1165. if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
  1166. dev_err(&data->i2c_client->dev,
  1167. "PLL configuration requires silabs,pll-m-den\n");
  1168. }
  1169. if (!m_num || !m_den) {
  1170. dev_err(&data->i2c_client->dev,
  1171. "PLL configuration invalid, assume 14GHz\n");
  1172. sel = si5341_clk_get_selected_input(data);
  1173. if (sel < 0)
  1174. return sel;
  1175. m_den = clk_get_rate(data->input_clk[sel]) / 10;
  1176. m_num = 1400000000;
  1177. }
  1178. return si5341_encode_44_32(data->regmap,
  1179. SI5341_PLL_M_NUM, m_num, m_den);
  1180. }
  1181. static int si5341_clk_select_active_input(struct clk_si5341 *data)
  1182. {
  1183. int res;
  1184. int err;
  1185. int i;
  1186. res = si5341_clk_get_selected_input(data);
  1187. if (res < 0)
  1188. return res;
  1189. /* If the current register setting is invalid, pick the first input */
  1190. if (!data->input_clk[res]) {
  1191. dev_dbg(&data->i2c_client->dev,
  1192. "Input %d not connected, rerouting\n", res);
  1193. res = -ENODEV;
  1194. for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
  1195. if (data->input_clk[i]) {
  1196. res = i;
  1197. break;
  1198. }
  1199. }
  1200. if (res < 0) {
  1201. dev_err(&data->i2c_client->dev,
  1202. "No clock input available\n");
  1203. return res;
  1204. }
  1205. }
  1206. /* Make sure the selected clock is also enabled and routed */
  1207. err = si5341_clk_reparent(data, res);
  1208. if (err < 0)
  1209. return err;
  1210. err = clk_prepare_enable(data->input_clk[res]);
  1211. if (err < 0)
  1212. return err;
  1213. return res;
  1214. }
  1215. static int si5341_probe(struct i2c_client *client,
  1216. const struct i2c_device_id *id)
  1217. {
  1218. struct clk_si5341 *data;
  1219. struct clk_init_data init;
  1220. struct clk *input;
  1221. const char *root_clock_name;
  1222. const char *synth_clock_names[SI5341_NUM_SYNTH];
  1223. int err;
  1224. unsigned int i;
  1225. struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
  1226. bool initialization_required;
  1227. u32 status;
  1228. data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
  1229. if (!data)
  1230. return -ENOMEM;
  1231. data->i2c_client = client;
  1232. /* Must be done before otherwise touching hardware */
  1233. err = si5341_wait_device_ready(client);
  1234. if (err)
  1235. return err;
  1236. for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
  1237. input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
  1238. if (IS_ERR(input)) {
  1239. if (PTR_ERR(input) == -EPROBE_DEFER)
  1240. return -EPROBE_DEFER;
  1241. data->input_clk_name[i] = si5341_input_clock_names[i];
  1242. } else {
  1243. data->input_clk[i] = input;
  1244. data->input_clk_name[i] = __clk_get_name(input);
  1245. }
  1246. }
  1247. err = si5341_dt_parse_dt(client, config);
  1248. if (err)
  1249. return err;
  1250. if (of_property_read_string(client->dev.of_node, "clock-output-names",
  1251. &init.name))
  1252. init.name = client->dev.of_node->name;
  1253. root_clock_name = init.name;
  1254. data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
  1255. if (IS_ERR(data->regmap))
  1256. return PTR_ERR(data->regmap);
  1257. i2c_set_clientdata(client, data);
  1258. err = si5341_probe_chip_id(data);
  1259. if (err < 0)
  1260. return err;
  1261. if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
  1262. initialization_required = true;
  1263. } else {
  1264. err = si5341_is_programmed_already(data);
  1265. if (err < 0)
  1266. return err;
  1267. initialization_required = !err;
  1268. }
  1269. if (initialization_required) {
  1270. /* Populate the regmap cache in preparation for "cache only" */
  1271. err = si5341_read_settings(data);
  1272. if (err < 0)
  1273. return err;
  1274. err = si5341_send_preamble(data);
  1275. if (err < 0)
  1276. return err;
  1277. /*
  1278. * We intend to send all 'final' register values in a single
  1279. * transaction. So cache all register writes until we're done
  1280. * configuring.
  1281. */
  1282. regcache_cache_only(data->regmap, true);
  1283. /* Write the configuration pairs from the firmware blob */
  1284. err = si5341_write_multiple(data, si5341_reg_defaults,
  1285. ARRAY_SIZE(si5341_reg_defaults));
  1286. if (err < 0)
  1287. return err;
  1288. }
  1289. /* Input must be up and running at this point */
  1290. err = si5341_clk_select_active_input(data);
  1291. if (err < 0)
  1292. return err;
  1293. if (initialization_required) {
  1294. /* PLL configuration is required */
  1295. err = si5341_initialize_pll(data);
  1296. if (err < 0)
  1297. return err;
  1298. }
  1299. /* Register the PLL */
  1300. init.parent_names = data->input_clk_name;
  1301. init.num_parents = SI5341_NUM_INPUTS;
  1302. init.ops = &si5341_clk_ops;
  1303. init.flags = 0;
  1304. data->hw.init = &init;
  1305. err = devm_clk_hw_register(&client->dev, &data->hw);
  1306. if (err) {
  1307. dev_err(&client->dev, "clock registration failed\n");
  1308. return err;
  1309. }
  1310. init.num_parents = 1;
  1311. init.parent_names = &root_clock_name;
  1312. init.ops = &si5341_synth_clk_ops;
  1313. for (i = 0; i < data->num_synth; ++i) {
  1314. synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
  1315. "%s.N%u", client->dev.of_node->name, i);
  1316. init.name = synth_clock_names[i];
  1317. data->synth[i].index = i;
  1318. data->synth[i].data = data;
  1319. data->synth[i].hw.init = &init;
  1320. err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
  1321. if (err) {
  1322. dev_err(&client->dev,
  1323. "synth N%u registration failed\n", i);
  1324. }
  1325. }
  1326. init.num_parents = data->num_synth;
  1327. init.parent_names = synth_clock_names;
  1328. init.ops = &si5341_output_clk_ops;
  1329. for (i = 0; i < data->num_outputs; ++i) {
  1330. init.name = kasprintf(GFP_KERNEL, "%s.%d",
  1331. client->dev.of_node->name, i);
  1332. init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
  1333. data->clk[i].index = i;
  1334. data->clk[i].data = data;
  1335. data->clk[i].hw.init = &init;
  1336. if (config[i].out_format_drv_bits & 0x07) {
  1337. regmap_write(data->regmap,
  1338. SI5341_OUT_FORMAT(&data->clk[i]),
  1339. config[i].out_format_drv_bits);
  1340. regmap_write(data->regmap,
  1341. SI5341_OUT_CM(&data->clk[i]),
  1342. config[i].out_cm_ampl_bits);
  1343. }
  1344. err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
  1345. kfree(init.name); /* clock framework made a copy of the name */
  1346. if (err) {
  1347. dev_err(&client->dev,
  1348. "output %u registration failed\n", i);
  1349. return err;
  1350. }
  1351. if (config[i].always_on)
  1352. clk_prepare(data->clk[i].hw.clk);
  1353. }
  1354. err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
  1355. data);
  1356. if (err) {
  1357. dev_err(&client->dev, "unable to add clk provider\n");
  1358. return err;
  1359. }
  1360. if (initialization_required) {
  1361. /* Synchronize */
  1362. regcache_cache_only(data->regmap, false);
  1363. err = regcache_sync(data->regmap);
  1364. if (err < 0)
  1365. return err;
  1366. err = si5341_finalize_defaults(data);
  1367. if (err < 0)
  1368. return err;
  1369. }
  1370. /* wait for device to report input clock present and PLL lock */
  1371. err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
  1372. !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
  1373. 10000, 250000);
  1374. if (err) {
  1375. dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
  1376. return err;
  1377. }
  1378. /* clear sticky alarm bits from initialization */
  1379. err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
  1380. if (err) {
  1381. dev_err(&client->dev, "unable to clear sticky status\n");
  1382. return err;
  1383. }
  1384. /* Free the names, clk framework makes copies */
  1385. for (i = 0; i < data->num_synth; ++i)
  1386. devm_kfree(&client->dev, (void *)synth_clock_names[i]);
  1387. return 0;
  1388. }
  1389. static const struct i2c_device_id si5341_id[] = {
  1390. { "si5340", 0 },
  1391. { "si5341", 1 },
  1392. { "si5342", 2 },
  1393. { "si5344", 4 },
  1394. { "si5345", 5 },
  1395. { }
  1396. };
  1397. MODULE_DEVICE_TABLE(i2c, si5341_id);
  1398. static const struct of_device_id clk_si5341_of_match[] = {
  1399. { .compatible = "silabs,si5340" },
  1400. { .compatible = "silabs,si5341" },
  1401. { .compatible = "silabs,si5342" },
  1402. { .compatible = "silabs,si5344" },
  1403. { .compatible = "silabs,si5345" },
  1404. { }
  1405. };
  1406. MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
  1407. static struct i2c_driver si5341_driver = {
  1408. .driver = {
  1409. .name = "si5341",
  1410. .of_match_table = clk_si5341_of_match,
  1411. },
  1412. .probe = si5341_probe,
  1413. .id_table = si5341_id,
  1414. };
  1415. module_i2c_driver(si5341_driver);
  1416. MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
  1417. MODULE_DESCRIPTION("Si5341 driver");
  1418. MODULE_LICENSE("GPL");