clk-oxnas.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010 Broadcom
  4. * Copyright (C) 2012 Stephen Warren
  5. * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/stringify.h>
  14. #include <linux/regmap.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <dt-bindings/clock/oxsemi,ox810se.h>
  17. #include <dt-bindings/clock/oxsemi,ox820.h>
  18. /* Standard regmap gate clocks */
  19. struct clk_oxnas_gate {
  20. struct clk_hw hw;
  21. unsigned int bit;
  22. struct regmap *regmap;
  23. };
  24. struct oxnas_stdclk_data {
  25. struct clk_hw_onecell_data *onecell_data;
  26. struct clk_oxnas_gate **gates;
  27. unsigned int ngates;
  28. struct clk_oxnas_pll **plls;
  29. unsigned int nplls;
  30. };
  31. /* Regmap offsets */
  32. #define CLK_STAT_REGOFFSET 0x24
  33. #define CLK_SET_REGOFFSET 0x2c
  34. #define CLK_CLR_REGOFFSET 0x30
  35. static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
  36. {
  37. return container_of(hw, struct clk_oxnas_gate, hw);
  38. }
  39. static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
  40. {
  41. struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
  42. int ret;
  43. unsigned int val;
  44. ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
  45. if (ret < 0)
  46. return ret;
  47. return val & BIT(std->bit);
  48. }
  49. static int oxnas_clk_gate_enable(struct clk_hw *hw)
  50. {
  51. struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
  52. regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
  53. return 0;
  54. }
  55. static void oxnas_clk_gate_disable(struct clk_hw *hw)
  56. {
  57. struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
  58. regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
  59. }
  60. static const struct clk_ops oxnas_clk_gate_ops = {
  61. .enable = oxnas_clk_gate_enable,
  62. .disable = oxnas_clk_gate_disable,
  63. .is_enabled = oxnas_clk_gate_is_enabled,
  64. };
  65. static const char *const osc_parents[] = {
  66. "oscillator",
  67. };
  68. static const char *const eth_parents[] = {
  69. "gmacclk",
  70. };
  71. #define OXNAS_GATE(_name, _bit, _parents) \
  72. struct clk_oxnas_gate _name = { \
  73. .bit = (_bit), \
  74. .hw.init = &(struct clk_init_data) { \
  75. .name = #_name, \
  76. .ops = &oxnas_clk_gate_ops, \
  77. .parent_names = _parents, \
  78. .num_parents = ARRAY_SIZE(_parents), \
  79. .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
  80. }, \
  81. }
  82. static OXNAS_GATE(ox810se_leon, 0, osc_parents);
  83. static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
  84. static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
  85. static OXNAS_GATE(ox810se_sata, 4, osc_parents);
  86. static OXNAS_GATE(ox810se_audio, 5, osc_parents);
  87. static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
  88. static OXNAS_GATE(ox810se_etha, 7, eth_parents);
  89. static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
  90. static OXNAS_GATE(ox810se_nand, 9, osc_parents);
  91. static struct clk_oxnas_gate *ox810se_gates[] = {
  92. &ox810se_leon,
  93. &ox810se_dma_sgdma,
  94. &ox810se_cipher,
  95. &ox810se_sata,
  96. &ox810se_audio,
  97. &ox810se_usbmph,
  98. &ox810se_etha,
  99. &ox810se_pciea,
  100. &ox810se_nand,
  101. };
  102. static OXNAS_GATE(ox820_leon, 0, osc_parents);
  103. static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
  104. static OXNAS_GATE(ox820_cipher, 2, osc_parents);
  105. static OXNAS_GATE(ox820_sd, 3, osc_parents);
  106. static OXNAS_GATE(ox820_sata, 4, osc_parents);
  107. static OXNAS_GATE(ox820_audio, 5, osc_parents);
  108. static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
  109. static OXNAS_GATE(ox820_etha, 7, eth_parents);
  110. static OXNAS_GATE(ox820_pciea, 8, osc_parents);
  111. static OXNAS_GATE(ox820_nand, 9, osc_parents);
  112. static OXNAS_GATE(ox820_ethb, 10, eth_parents);
  113. static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
  114. static OXNAS_GATE(ox820_ref600, 12, osc_parents);
  115. static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
  116. static struct clk_oxnas_gate *ox820_gates[] = {
  117. &ox820_leon,
  118. &ox820_dma_sgdma,
  119. &ox820_cipher,
  120. &ox820_sd,
  121. &ox820_sata,
  122. &ox820_audio,
  123. &ox820_usbmph,
  124. &ox820_etha,
  125. &ox820_pciea,
  126. &ox820_nand,
  127. &ox820_etha,
  128. &ox820_pciea,
  129. &ox820_ref600,
  130. &ox820_usbdev,
  131. };
  132. static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
  133. .hws = {
  134. [CLK_810_LEON] = &ox810se_leon.hw,
  135. [CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
  136. [CLK_810_CIPHER] = &ox810se_cipher.hw,
  137. [CLK_810_SATA] = &ox810se_sata.hw,
  138. [CLK_810_AUDIO] = &ox810se_audio.hw,
  139. [CLK_810_USBMPH] = &ox810se_usbmph.hw,
  140. [CLK_810_ETHA] = &ox810se_etha.hw,
  141. [CLK_810_PCIEA] = &ox810se_pciea.hw,
  142. [CLK_810_NAND] = &ox810se_nand.hw,
  143. },
  144. .num = ARRAY_SIZE(ox810se_gates),
  145. };
  146. static struct clk_hw_onecell_data ox820_hw_onecell_data = {
  147. .hws = {
  148. [CLK_820_LEON] = &ox820_leon.hw,
  149. [CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw,
  150. [CLK_820_CIPHER] = &ox820_cipher.hw,
  151. [CLK_820_SD] = &ox820_sd.hw,
  152. [CLK_820_SATA] = &ox820_sata.hw,
  153. [CLK_820_AUDIO] = &ox820_audio.hw,
  154. [CLK_820_USBMPH] = &ox820_usbmph.hw,
  155. [CLK_820_ETHA] = &ox820_etha.hw,
  156. [CLK_820_PCIEA] = &ox820_pciea.hw,
  157. [CLK_820_NAND] = &ox820_nand.hw,
  158. [CLK_820_ETHB] = &ox820_ethb.hw,
  159. [CLK_820_PCIEB] = &ox820_pcieb.hw,
  160. [CLK_820_REF600] = &ox820_ref600.hw,
  161. [CLK_820_USBDEV] = &ox820_usbdev.hw,
  162. },
  163. .num = ARRAY_SIZE(ox820_gates),
  164. };
  165. static struct oxnas_stdclk_data ox810se_stdclk_data = {
  166. .onecell_data = &ox810se_hw_onecell_data,
  167. .gates = ox810se_gates,
  168. .ngates = ARRAY_SIZE(ox810se_gates),
  169. };
  170. static struct oxnas_stdclk_data ox820_stdclk_data = {
  171. .onecell_data = &ox820_hw_onecell_data,
  172. .gates = ox820_gates,
  173. .ngates = ARRAY_SIZE(ox820_gates),
  174. };
  175. static const struct of_device_id oxnas_stdclk_dt_ids[] = {
  176. { .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
  177. { .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
  178. { }
  179. };
  180. static int oxnas_stdclk_probe(struct platform_device *pdev)
  181. {
  182. struct device_node *np = pdev->dev.of_node;
  183. const struct oxnas_stdclk_data *data;
  184. const struct of_device_id *id;
  185. struct regmap *regmap;
  186. int ret;
  187. int i;
  188. id = of_match_device(oxnas_stdclk_dt_ids, &pdev->dev);
  189. if (!id)
  190. return -ENODEV;
  191. data = id->data;
  192. regmap = syscon_node_to_regmap(of_get_parent(np));
  193. if (IS_ERR(regmap)) {
  194. dev_err(&pdev->dev, "failed to have parent regmap\n");
  195. return PTR_ERR(regmap);
  196. }
  197. for (i = 0 ; i < data->ngates ; ++i)
  198. data->gates[i]->regmap = regmap;
  199. for (i = 0; i < data->onecell_data->num; i++) {
  200. if (!data->onecell_data->hws[i])
  201. continue;
  202. ret = devm_clk_hw_register(&pdev->dev,
  203. data->onecell_data->hws[i]);
  204. if (ret)
  205. return ret;
  206. }
  207. return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
  208. data->onecell_data);
  209. }
  210. static struct platform_driver oxnas_stdclk_driver = {
  211. .probe = oxnas_stdclk_probe,
  212. .driver = {
  213. .name = "oxnas-stdclk",
  214. .suppress_bind_attrs = true,
  215. .of_match_table = oxnas_stdclk_dt_ids,
  216. },
  217. };
  218. builtin_platform_driver(oxnas_stdclk_driver);