clk-nspire.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #define MHZ (1000 * 1000)
  12. #define BASE_CPU_SHIFT 1
  13. #define BASE_CPU_MASK 0x7F
  14. #define CPU_AHB_SHIFT 12
  15. #define CPU_AHB_MASK 0x07
  16. #define FIXED_BASE_SHIFT 8
  17. #define FIXED_BASE_MASK 0x01
  18. #define CLASSIC_BASE_SHIFT 16
  19. #define CLASSIC_BASE_MASK 0x1F
  20. #define CX_BASE_SHIFT 15
  21. #define CX_BASE_MASK 0x3F
  22. #define CX_UNKNOWN_SHIFT 21
  23. #define CX_UNKNOWN_MASK 0x03
  24. struct nspire_clk_info {
  25. u32 base_clock;
  26. u16 base_cpu_ratio;
  27. u16 base_ahb_ratio;
  28. };
  29. #define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)
  30. static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk)
  31. {
  32. if (EXTRACT(val, FIXED_BASE))
  33. clk->base_clock = 48 * MHZ;
  34. else
  35. clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
  36. clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN);
  37. clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
  38. }
  39. static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk)
  40. {
  41. if (EXTRACT(val, FIXED_BASE))
  42. clk->base_clock = 27 * MHZ;
  43. else
  44. clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
  45. clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2;
  46. clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
  47. }
  48. static void __init nspire_ahbdiv_setup(struct device_node *node,
  49. void (*get_clkinfo)(u32, struct nspire_clk_info *))
  50. {
  51. u32 val;
  52. void __iomem *io;
  53. struct clk_hw *hw;
  54. const char *clk_name = node->name;
  55. const char *parent_name;
  56. struct nspire_clk_info info;
  57. io = of_iomap(node, 0);
  58. if (!io)
  59. return;
  60. val = readl(io);
  61. iounmap(io);
  62. get_clkinfo(val, &info);
  63. of_property_read_string(node, "clock-output-names", &clk_name);
  64. parent_name = of_clk_get_parent_name(node, 0);
  65. hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0,
  66. 1, info.base_ahb_ratio);
  67. if (!IS_ERR(hw))
  68. of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
  69. }
  70. static void __init nspire_ahbdiv_setup_cx(struct device_node *node)
  71. {
  72. nspire_ahbdiv_setup(node, nspire_clkinfo_cx);
  73. }
  74. static void __init nspire_ahbdiv_setup_classic(struct device_node *node)
  75. {
  76. nspire_ahbdiv_setup(node, nspire_clkinfo_classic);
  77. }
  78. CLK_OF_DECLARE(nspire_ahbdiv_cx, "lsi,nspire-cx-ahb-divider",
  79. nspire_ahbdiv_setup_cx);
  80. CLK_OF_DECLARE(nspire_ahbdiv_classic, "lsi,nspire-classic-ahb-divider",
  81. nspire_ahbdiv_setup_classic);
  82. static void __init nspire_clk_setup(struct device_node *node,
  83. void (*get_clkinfo)(u32, struct nspire_clk_info *))
  84. {
  85. u32 val;
  86. void __iomem *io;
  87. struct clk_hw *hw;
  88. const char *clk_name = node->name;
  89. struct nspire_clk_info info;
  90. io = of_iomap(node, 0);
  91. if (!io)
  92. return;
  93. val = readl(io);
  94. iounmap(io);
  95. get_clkinfo(val, &info);
  96. of_property_read_string(node, "clock-output-names", &clk_name);
  97. hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0,
  98. info.base_clock);
  99. if (!IS_ERR(hw))
  100. of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
  101. else
  102. return;
  103. pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n",
  104. info.base_clock / MHZ,
  105. info.base_clock / info.base_cpu_ratio / MHZ,
  106. info.base_clock / info.base_ahb_ratio / MHZ);
  107. }
  108. static void __init nspire_clk_setup_cx(struct device_node *node)
  109. {
  110. nspire_clk_setup(node, nspire_clkinfo_cx);
  111. }
  112. static void __init nspire_clk_setup_classic(struct device_node *node)
  113. {
  114. nspire_clk_setup(node, nspire_clkinfo_classic);
  115. }
  116. CLK_OF_DECLARE(nspire_clk_cx, "lsi,nspire-cx-clock", nspire_clk_setup_cx);
  117. CLK_OF_DECLARE(nspire_clk_classic, "lsi,nspire-classic-clock",
  118. nspire_clk_setup_classic);