clk-npcm7xx.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Nuvoton NPCM7xx Clock Generator
  4. * All the clocks are initialized by the bootloader, so this driver allow only
  5. * reading of current settings directly from the hardware.
  6. *
  7. * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
  8. */
  9. #include <linux/module.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/slab.h>
  16. #include <linux/err.h>
  17. #include <linux/bitfield.h>
  18. #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
  19. struct npcm7xx_clk_pll {
  20. struct clk_hw hw;
  21. void __iomem *pllcon;
  22. u8 flags;
  23. };
  24. #define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
  25. #define PLLCON_LOKI BIT(31)
  26. #define PLLCON_LOKS BIT(30)
  27. #define PLLCON_FBDV GENMASK(27, 16)
  28. #define PLLCON_OTDV2 GENMASK(15, 13)
  29. #define PLLCON_PWDEN BIT(12)
  30. #define PLLCON_OTDV1 GENMASK(10, 8)
  31. #define PLLCON_INDV GENMASK(5, 0)
  32. static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
  33. unsigned long parent_rate)
  34. {
  35. struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
  36. unsigned long fbdv, indv, otdv1, otdv2;
  37. unsigned int val;
  38. u64 ret;
  39. if (parent_rate == 0) {
  40. pr_err("%s: parent rate is zero", __func__);
  41. return 0;
  42. }
  43. val = readl_relaxed(pll->pllcon);
  44. indv = FIELD_GET(PLLCON_INDV, val);
  45. fbdv = FIELD_GET(PLLCON_FBDV, val);
  46. otdv1 = FIELD_GET(PLLCON_OTDV1, val);
  47. otdv2 = FIELD_GET(PLLCON_OTDV2, val);
  48. ret = (u64)parent_rate * fbdv;
  49. do_div(ret, indv * otdv1 * otdv2);
  50. return ret;
  51. }
  52. static const struct clk_ops npcm7xx_clk_pll_ops = {
  53. .recalc_rate = npcm7xx_clk_pll_recalc_rate,
  54. };
  55. static struct clk_hw *
  56. npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
  57. const char *parent_name, unsigned long flags)
  58. {
  59. struct npcm7xx_clk_pll *pll;
  60. struct clk_init_data init;
  61. struct clk_hw *hw;
  62. int ret;
  63. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  64. if (!pll)
  65. return ERR_PTR(-ENOMEM);
  66. pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
  67. init.name = name;
  68. init.ops = &npcm7xx_clk_pll_ops;
  69. init.parent_names = &parent_name;
  70. init.num_parents = 1;
  71. init.flags = flags;
  72. pll->pllcon = pllcon;
  73. pll->hw.init = &init;
  74. hw = &pll->hw;
  75. ret = clk_hw_register(NULL, hw);
  76. if (ret) {
  77. kfree(pll);
  78. hw = ERR_PTR(ret);
  79. }
  80. return hw;
  81. }
  82. #define NPCM7XX_CLKEN1 (0x00)
  83. #define NPCM7XX_CLKEN2 (0x28)
  84. #define NPCM7XX_CLKEN3 (0x30)
  85. #define NPCM7XX_CLKSEL (0x04)
  86. #define NPCM7XX_CLKDIV1 (0x08)
  87. #define NPCM7XX_CLKDIV2 (0x2C)
  88. #define NPCM7XX_CLKDIV3 (0x58)
  89. #define NPCM7XX_PLLCON0 (0x0C)
  90. #define NPCM7XX_PLLCON1 (0x10)
  91. #define NPCM7XX_PLLCON2 (0x54)
  92. #define NPCM7XX_SWRSTR (0x14)
  93. #define NPCM7XX_IRQWAKECON (0x18)
  94. #define NPCM7XX_IRQWAKEFLAG (0x1C)
  95. #define NPCM7XX_IPSRST1 (0x20)
  96. #define NPCM7XX_IPSRST2 (0x24)
  97. #define NPCM7XX_IPSRST3 (0x34)
  98. #define NPCM7XX_WD0RCR (0x38)
  99. #define NPCM7XX_WD1RCR (0x3C)
  100. #define NPCM7XX_WD2RCR (0x40)
  101. #define NPCM7XX_SWRSTC1 (0x44)
  102. #define NPCM7XX_SWRSTC2 (0x48)
  103. #define NPCM7XX_SWRSTC3 (0x4C)
  104. #define NPCM7XX_SWRSTC4 (0x50)
  105. #define NPCM7XX_CORSTC (0x5C)
  106. #define NPCM7XX_PLLCONG (0x60)
  107. #define NPCM7XX_AHBCKFI (0x64)
  108. #define NPCM7XX_SECCNT (0x68)
  109. #define NPCM7XX_CNTR25M (0x6C)
  110. struct npcm7xx_clk_gate_data {
  111. u32 reg;
  112. u8 bit_idx;
  113. const char *name;
  114. const char *parent_name;
  115. unsigned long flags;
  116. /*
  117. * If this clock is exported via DT, set onecell_idx to constant
  118. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  119. * this specific clock. Otherwise, set to -1.
  120. */
  121. int onecell_idx;
  122. };
  123. struct npcm7xx_clk_mux_data {
  124. u8 shift;
  125. u8 mask;
  126. u32 *table;
  127. const char *name;
  128. const char * const *parent_names;
  129. u8 num_parents;
  130. unsigned long flags;
  131. /*
  132. * If this clock is exported via DT, set onecell_idx to constant
  133. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  134. * this specific clock. Otherwise, set to -1.
  135. */
  136. int onecell_idx;
  137. };
  138. struct npcm7xx_clk_div_fixed_data {
  139. u8 mult;
  140. u8 div;
  141. const char *name;
  142. const char *parent_name;
  143. u8 clk_divider_flags;
  144. /*
  145. * If this clock is exported via DT, set onecell_idx to constant
  146. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  147. * this specific clock. Otherwise, set to -1.
  148. */
  149. int onecell_idx;
  150. };
  151. struct npcm7xx_clk_div_data {
  152. u32 reg;
  153. u8 shift;
  154. u8 width;
  155. const char *name;
  156. const char *parent_name;
  157. u8 clk_divider_flags;
  158. unsigned long flags;
  159. /*
  160. * If this clock is exported via DT, set onecell_idx to constant
  161. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  162. * this specific clock. Otherwise, set to -1.
  163. */
  164. int onecell_idx;
  165. };
  166. struct npcm7xx_clk_pll_data {
  167. u32 reg;
  168. const char *name;
  169. const char *parent_name;
  170. unsigned long flags;
  171. /*
  172. * If this clock is exported via DT, set onecell_idx to constant
  173. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  174. * this specific clock. Otherwise, set to -1.
  175. */
  176. int onecell_idx;
  177. };
  178. /*
  179. * Single copy of strings used to refer to clocks within this driver indexed by
  180. * above enum.
  181. */
  182. #define NPCM7XX_CLK_S_REFCLK "refclk"
  183. #define NPCM7XX_CLK_S_SYSBYPCK "sysbypck"
  184. #define NPCM7XX_CLK_S_MCBYPCK "mcbypck"
  185. #define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck"
  186. #define NPCM7XX_CLK_S_PLL0 "pll0"
  187. #define NPCM7XX_CLK_S_PLL1 "pll1"
  188. #define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2"
  189. #define NPCM7XX_CLK_S_PLL2 "pll2"
  190. #define NPCM7XX_CLK_S_PLL_GFX "pll_gfx"
  191. #define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2"
  192. #define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel"
  193. #define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
  194. #define NPCM7XX_CLK_S_MC_MUX "mc_phy"
  195. #define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/
  196. #define NPCM7XX_CLK_S_MC "mc"
  197. #define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/
  198. #define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/
  199. #define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux"
  200. #define NPCM7XX_CLK_S_UART_MUX "uart_mux"
  201. #define NPCM7XX_CLK_S_TIM_MUX "timer_mux"
  202. #define NPCM7XX_CLK_S_SD_MUX "sd_mux"
  203. #define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux"
  204. #define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux"
  205. #define NPCM7XX_CLK_S_DVC_MUX "dvc_mux"
  206. #define NPCM7XX_CLK_S_GFX_MUX "gfx_mux"
  207. #define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel"
  208. #define NPCM7XX_CLK_S_SPI0 "spi0"
  209. #define NPCM7XX_CLK_S_SPI3 "spi3"
  210. #define NPCM7XX_CLK_S_SPIX "spix"
  211. #define NPCM7XX_CLK_S_APB1 "apb1"
  212. #define NPCM7XX_CLK_S_APB2 "apb2"
  213. #define NPCM7XX_CLK_S_APB3 "apb3"
  214. #define NPCM7XX_CLK_S_APB4 "apb4"
  215. #define NPCM7XX_CLK_S_APB5 "apb5"
  216. #define NPCM7XX_CLK_S_TOCK "tock"
  217. #define NPCM7XX_CLK_S_CLKOUT "clkout"
  218. #define NPCM7XX_CLK_S_UART "uart"
  219. #define NPCM7XX_CLK_S_TIMER "timer"
  220. #define NPCM7XX_CLK_S_MMC "mmc"
  221. #define NPCM7XX_CLK_S_SDHC "sdhc"
  222. #define NPCM7XX_CLK_S_ADC "adc"
  223. #define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem"
  224. #define NPCM7XX_CLK_S_USBIF "serial_usbif"
  225. #define NPCM7XX_CLK_S_USB_HOST "usb_host"
  226. #define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge"
  227. #define NPCM7XX_CLK_S_PCI "pci"
  228. static u32 pll_mux_table[] = {0, 1, 2, 3};
  229. static const char * const pll_mux_parents[] __initconst = {
  230. NPCM7XX_CLK_S_PLL0,
  231. NPCM7XX_CLK_S_PLL1_DIV2,
  232. NPCM7XX_CLK_S_REFCLK,
  233. NPCM7XX_CLK_S_PLL2_DIV2,
  234. };
  235. static u32 cpuck_mux_table[] = {0, 1, 2, 3};
  236. static const char * const cpuck_mux_parents[] __initconst = {
  237. NPCM7XX_CLK_S_PLL0,
  238. NPCM7XX_CLK_S_PLL1_DIV2,
  239. NPCM7XX_CLK_S_REFCLK,
  240. NPCM7XX_CLK_S_SYSBYPCK,
  241. };
  242. static u32 pixcksel_mux_table[] = {0, 2};
  243. static const char * const pixcksel_mux_parents[] __initconst = {
  244. NPCM7XX_CLK_S_PLL_GFX,
  245. NPCM7XX_CLK_S_REFCLK,
  246. };
  247. static u32 sucksel_mux_table[] = {2, 3};
  248. static const char * const sucksel_mux_parents[] __initconst = {
  249. NPCM7XX_CLK_S_REFCLK,
  250. NPCM7XX_CLK_S_PLL2_DIV2,
  251. };
  252. static u32 mccksel_mux_table[] = {0, 2, 3};
  253. static const char * const mccksel_mux_parents[] __initconst = {
  254. NPCM7XX_CLK_S_PLL1_DIV2,
  255. NPCM7XX_CLK_S_REFCLK,
  256. NPCM7XX_CLK_S_MCBYPCK,
  257. };
  258. static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
  259. static const char * const clkoutsel_mux_parents[] __initconst = {
  260. NPCM7XX_CLK_S_PLL0,
  261. NPCM7XX_CLK_S_PLL1_DIV2,
  262. NPCM7XX_CLK_S_REFCLK,
  263. NPCM7XX_CLK_S_PLL_GFX, // divided by 2
  264. NPCM7XX_CLK_S_PLL2_DIV2,
  265. };
  266. static u32 gfxmsel_mux_table[] = {2, 3};
  267. static const char * const gfxmsel_mux_parents[] __initconst = {
  268. NPCM7XX_CLK_S_REFCLK,
  269. NPCM7XX_CLK_S_PLL2_DIV2,
  270. };
  271. static u32 dvcssel_mux_table[] = {2, 3};
  272. static const char * const dvcssel_mux_parents[] __initconst = {
  273. NPCM7XX_CLK_S_REFCLK,
  274. NPCM7XX_CLK_S_PLL2,
  275. };
  276. static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
  277. {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
  278. {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
  279. NPCM7XX_CLK_S_REFCLK, 0, -1},
  280. {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
  281. NPCM7XX_CLK_S_REFCLK, 0, -1},
  282. {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
  283. NPCM7XX_CLK_S_REFCLK, 0, -1},
  284. };
  285. static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
  286. {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
  287. cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
  288. NPCM7XX_CLK_CPU},
  289. {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
  290. pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
  291. NPCM7XX_CLK_GFX_PIXEL},
  292. {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
  293. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  294. {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
  295. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  296. {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
  297. sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
  298. {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
  299. mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
  300. {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
  301. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  302. {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
  303. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  304. {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
  305. clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
  306. {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
  307. gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
  308. {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
  309. dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
  310. };
  311. /* fixed ratio dividers (no register): */
  312. static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
  313. { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
  314. { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
  315. { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
  316. };
  317. /* configurable dividers: */
  318. static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
  319. {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
  320. NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
  321. /*30-28 ADCCKDIV*/
  322. {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
  323. NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
  324. /*27-26 CLK4DIV*/
  325. {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
  326. NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
  327. /*25-21 TIMCKDIV*/
  328. {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
  329. NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
  330. /*20-16 UARTDIV*/
  331. {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
  332. NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
  333. /*15-11 MMCCKDIV*/
  334. {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
  335. NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
  336. /*10-6 AHB3CKDIV*/
  337. {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
  338. NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
  339. /*5-2 PCICKDIV*/
  340. {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
  341. NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
  342. NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
  343. {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
  344. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
  345. /*31-30 APB4CKDIV*/
  346. {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
  347. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
  348. /*29-28 APB3CKDIV*/
  349. {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
  350. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
  351. /*27-26 APB2CKDIV*/
  352. {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
  353. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
  354. /*25-24 APB1CKDIV*/
  355. {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
  356. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
  357. /*23-22 APB5CKDIV*/
  358. {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
  359. NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
  360. /*20-16 CLKOUTDIV*/
  361. {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
  362. NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
  363. /*15-13 GFXCKDIV*/
  364. {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
  365. NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
  366. /*12-8 SUCKDIV*/
  367. {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
  368. NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
  369. /*7-4 SU48CKDIV*/
  370. {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
  371. NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
  372. ,/*3-0 SD1CKDIV*/
  373. {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
  374. NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
  375. /*10-6 SPI0CKDV*/
  376. {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
  377. NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
  378. /*5-1 SPIXCKDV*/
  379. };
  380. static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
  381. {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
  382. {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
  383. {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
  384. {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
  385. {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
  386. {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
  387. {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
  388. {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
  389. {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
  390. {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
  391. {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
  392. {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
  393. {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
  394. {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
  395. {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
  396. {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
  397. {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
  398. {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
  399. {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
  400. {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
  401. {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
  402. {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
  403. {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
  404. {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
  405. {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
  406. {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
  407. {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
  408. {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
  409. /* bit 3 is reserved */
  410. {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
  411. {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
  412. {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
  413. {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
  414. {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
  415. /* bit 29 is reserved */
  416. {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
  417. {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
  418. {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
  419. {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
  420. /* bit 24 is reserved */
  421. {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
  422. {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
  423. {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
  424. /* bit 20 is reserved */
  425. {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
  426. {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
  427. /* bit 17 is reserved */
  428. {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
  429. /* bit 15 is reserved */
  430. {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
  431. {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
  432. {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
  433. {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
  434. {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
  435. {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
  436. {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
  437. {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
  438. {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
  439. {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
  440. {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
  441. {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
  442. {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
  443. {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
  444. {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
  445. {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
  446. {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
  447. {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
  448. {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
  449. {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
  450. {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
  451. {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
  452. {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
  453. {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
  454. {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
  455. {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
  456. {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
  457. {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
  458. {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
  459. {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
  460. {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
  461. {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
  462. {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
  463. {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
  464. {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
  465. /* bit 11 is reserved */
  466. /* bit 10 is reserved */
  467. {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
  468. /* bit 8 is reserved */
  469. {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
  470. {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
  471. {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
  472. {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
  473. {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
  474. {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
  475. {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
  476. {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
  477. };
  478. static DEFINE_SPINLOCK(npcm7xx_clk_lock);
  479. static void __init npcm7xx_clk_init(struct device_node *clk_np)
  480. {
  481. struct clk_hw_onecell_data *npcm7xx_clk_data;
  482. void __iomem *clk_base;
  483. struct resource res;
  484. struct clk_hw *hw;
  485. int ret;
  486. int i;
  487. ret = of_address_to_resource(clk_np, 0, &res);
  488. if (ret) {
  489. pr_err("%pOFn: failed to get resource, ret %d\n", clk_np,
  490. ret);
  491. return;
  492. }
  493. clk_base = ioremap(res.start, resource_size(&res));
  494. if (!clk_base)
  495. goto npcm7xx_init_error;
  496. npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws,
  497. NPCM7XX_NUM_CLOCKS), GFP_KERNEL);
  498. if (!npcm7xx_clk_data)
  499. goto npcm7xx_init_np_err;
  500. npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
  501. for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
  502. npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
  503. /* Register plls */
  504. for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
  505. const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
  506. hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
  507. pll_data->name, pll_data->parent_name, pll_data->flags);
  508. if (IS_ERR(hw)) {
  509. pr_err("npcm7xx_clk: Can't register pll\n");
  510. goto npcm7xx_init_fail;
  511. }
  512. if (pll_data->onecell_idx >= 0)
  513. npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
  514. }
  515. /* Register fixed dividers */
  516. hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
  517. NPCM7XX_CLK_S_PLL1, 0, 1, 2);
  518. if (IS_ERR(hw)) {
  519. pr_err("npcm7xx_clk: Can't register fixed div\n");
  520. goto npcm7xx_init_fail;
  521. }
  522. hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
  523. NPCM7XX_CLK_S_PLL2, 0, 1, 2);
  524. if (IS_ERR(hw)) {
  525. pr_err("npcm7xx_clk: Can't register div2\n");
  526. goto npcm7xx_init_fail;
  527. }
  528. /* Register muxes */
  529. for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
  530. const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
  531. hw = clk_hw_register_mux_table(NULL,
  532. mux_data->name,
  533. mux_data->parent_names, mux_data->num_parents,
  534. mux_data->flags, clk_base + NPCM7XX_CLKSEL,
  535. mux_data->shift, mux_data->mask, 0,
  536. mux_data->table, &npcm7xx_clk_lock);
  537. if (IS_ERR(hw)) {
  538. pr_err("npcm7xx_clk: Can't register mux\n");
  539. goto npcm7xx_init_fail;
  540. }
  541. if (mux_data->onecell_idx >= 0)
  542. npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
  543. }
  544. /* Register clock dividers specified in npcm7xx_divs */
  545. for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
  546. const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
  547. hw = clk_hw_register_divider(NULL, div_data->name,
  548. div_data->parent_name,
  549. div_data->flags,
  550. clk_base + div_data->reg,
  551. div_data->shift, div_data->width,
  552. div_data->clk_divider_flags, &npcm7xx_clk_lock);
  553. if (IS_ERR(hw)) {
  554. pr_err("npcm7xx_clk: Can't register div table\n");
  555. goto npcm7xx_init_fail;
  556. }
  557. if (div_data->onecell_idx >= 0)
  558. npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
  559. }
  560. ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
  561. npcm7xx_clk_data);
  562. if (ret)
  563. pr_err("failed to add DT provider: %d\n", ret);
  564. of_node_put(clk_np);
  565. return;
  566. npcm7xx_init_fail:
  567. kfree(npcm7xx_clk_data->hws);
  568. npcm7xx_init_np_err:
  569. iounmap(clk_base);
  570. npcm7xx_init_error:
  571. of_node_put(clk_np);
  572. }
  573. CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);