clk-milbeaut.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Socionext Inc.
  4. * Copyright (C) 2016 Linaro Ltd.
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/of_address.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/slab.h>
  13. #include <linux/spinlock.h>
  14. #define M10V_CLKSEL1 0x0
  15. #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
  16. #define M10V_PLL1 "pll1"
  17. #define M10V_PLL1DIV2 "pll1-2"
  18. #define M10V_PLL2 "pll2"
  19. #define M10V_PLL2DIV2 "pll2-2"
  20. #define M10V_PLL6 "pll6"
  21. #define M10V_PLL6DIV2 "pll6-2"
  22. #define M10V_PLL6DIV3 "pll6-3"
  23. #define M10V_PLL7 "pll7"
  24. #define M10V_PLL7DIV2 "pll7-2"
  25. #define M10V_PLL7DIV5 "pll7-5"
  26. #define M10V_PLL9 "pll9"
  27. #define M10V_PLL10 "pll10"
  28. #define M10V_PLL10DIV2 "pll10-2"
  29. #define M10V_PLL11 "pll11"
  30. #define M10V_SPI_PARENT0 "spi-parent0"
  31. #define M10V_SPI_PARENT1 "spi-parent1"
  32. #define M10V_SPI_PARENT2 "spi-parent2"
  33. #define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
  34. #define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
  35. #define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
  36. #define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
  37. #define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
  38. #define M10V_NFCLK_PARENT0 "nfclk-parent0"
  39. #define M10V_NFCLK_PARENT1 "nfclk-parent1"
  40. #define M10V_NFCLK_PARENT2 "nfclk-parent2"
  41. #define M10V_NFCLK_PARENT3 "nfclk-parent3"
  42. #define M10V_NFCLK_PARENT4 "nfclk-parent4"
  43. #define M10V_NFCLK_PARENT5 "nfclk-parent5"
  44. #define M10V_DCHREQ 1
  45. #define M10V_UPOLL_RATE 1
  46. #define M10V_UTIMEOUT 250
  47. #define M10V_EMMCCLK_ID 0
  48. #define M10V_ACLK_ID 1
  49. #define M10V_HCLK_ID 2
  50. #define M10V_PCLK_ID 3
  51. #define M10V_RCLK_ID 4
  52. #define M10V_SPICLK_ID 5
  53. #define M10V_NFCLK_ID 6
  54. #define M10V_UHS1CLK2_ID 7
  55. #define M10V_NUM_CLKS 8
  56. #define to_m10v_div(_hw) container_of(_hw, struct m10v_clk_divider, hw)
  57. static struct clk_hw_onecell_data *m10v_clk_data;
  58. static DEFINE_SPINLOCK(m10v_crglock);
  59. struct m10v_clk_div_factors {
  60. const char *name;
  61. const char *parent_name;
  62. u32 offset;
  63. u8 shift;
  64. u8 width;
  65. const struct clk_div_table *table;
  66. unsigned long div_flags;
  67. int onecell_idx;
  68. };
  69. struct m10v_clk_div_fixed_data {
  70. const char *name;
  71. const char *parent_name;
  72. u8 div;
  73. u8 mult;
  74. int onecell_idx;
  75. };
  76. struct m10v_clk_mux_factors {
  77. const char *name;
  78. const char * const *parent_names;
  79. u8 num_parents;
  80. u32 offset;
  81. u8 shift;
  82. u8 mask;
  83. u32 *table;
  84. unsigned long mux_flags;
  85. int onecell_idx;
  86. };
  87. static const struct clk_div_table emmcclk_table[] = {
  88. { .val = 0, .div = 8 },
  89. { .val = 1, .div = 9 },
  90. { .val = 2, .div = 10 },
  91. { .val = 3, .div = 15 },
  92. { .div = 0 },
  93. };
  94. static const struct clk_div_table mclk400_table[] = {
  95. { .val = 1, .div = 2 },
  96. { .val = 3, .div = 4 },
  97. { .div = 0 },
  98. };
  99. static const struct clk_div_table mclk200_table[] = {
  100. { .val = 3, .div = 4 },
  101. { .val = 7, .div = 8 },
  102. { .div = 0 },
  103. };
  104. static const struct clk_div_table aclk400_table[] = {
  105. { .val = 1, .div = 2 },
  106. { .val = 3, .div = 4 },
  107. { .div = 0 },
  108. };
  109. static const struct clk_div_table aclk300_table[] = {
  110. { .val = 0, .div = 2 },
  111. { .val = 1, .div = 3 },
  112. { .div = 0 },
  113. };
  114. static const struct clk_div_table aclk_table[] = {
  115. { .val = 3, .div = 4 },
  116. { .val = 7, .div = 8 },
  117. { .div = 0 },
  118. };
  119. static const struct clk_div_table aclkexs_table[] = {
  120. { .val = 3, .div = 4 },
  121. { .val = 4, .div = 5 },
  122. { .val = 5, .div = 6 },
  123. { .val = 7, .div = 8 },
  124. { .div = 0 },
  125. };
  126. static const struct clk_div_table hclk_table[] = {
  127. { .val = 7, .div = 8 },
  128. { .val = 15, .div = 16 },
  129. { .div = 0 },
  130. };
  131. static const struct clk_div_table hclkbmh_table[] = {
  132. { .val = 3, .div = 4 },
  133. { .val = 7, .div = 8 },
  134. { .div = 0 },
  135. };
  136. static const struct clk_div_table pclk_table[] = {
  137. { .val = 15, .div = 16 },
  138. { .val = 31, .div = 32 },
  139. { .div = 0 },
  140. };
  141. static const struct clk_div_table rclk_table[] = {
  142. { .val = 0, .div = 8 },
  143. { .val = 1, .div = 16 },
  144. { .val = 2, .div = 24 },
  145. { .val = 3, .div = 32 },
  146. { .div = 0 },
  147. };
  148. static const struct clk_div_table uhs1clk0_table[] = {
  149. { .val = 0, .div = 2 },
  150. { .val = 1, .div = 3 },
  151. { .val = 2, .div = 4 },
  152. { .val = 3, .div = 8 },
  153. { .val = 4, .div = 16 },
  154. { .div = 0 },
  155. };
  156. static const struct clk_div_table uhs2clk_table[] = {
  157. { .val = 0, .div = 9 },
  158. { .val = 1, .div = 10 },
  159. { .val = 2, .div = 11 },
  160. { .val = 3, .div = 12 },
  161. { .val = 4, .div = 13 },
  162. { .val = 5, .div = 14 },
  163. { .val = 6, .div = 16 },
  164. { .val = 7, .div = 18 },
  165. { .div = 0 },
  166. };
  167. static u32 spi_mux_table[] = {0, 1, 2};
  168. static const char * const spi_mux_names[] = {
  169. M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
  170. };
  171. static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
  172. static const char * const uhs1clk2_mux_names[] = {
  173. M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
  174. M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
  175. };
  176. static u32 uhs1clk1_mux_table[] = {3, 4, 8};
  177. static const char * const uhs1clk1_mux_names[] = {
  178. M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
  179. };
  180. static u32 nfclk_mux_table[] = {0, 1, 2, 3, 4, 8};
  181. static const char * const nfclk_mux_names[] = {
  182. M10V_NFCLK_PARENT0, M10V_NFCLK_PARENT1, M10V_NFCLK_PARENT2,
  183. M10V_NFCLK_PARENT3, M10V_NFCLK_PARENT4, M10V_NFCLK_PARENT5
  184. };
  185. static const struct m10v_clk_div_fixed_data m10v_pll_fixed_data[] = {
  186. {M10V_PLL1, NULL, 1, 40, -1},
  187. {M10V_PLL2, NULL, 1, 30, -1},
  188. {M10V_PLL6, NULL, 1, 35, -1},
  189. {M10V_PLL7, NULL, 1, 40, -1},
  190. {M10V_PLL9, NULL, 1, 33, -1},
  191. {M10V_PLL10, NULL, 5, 108, -1},
  192. {M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1},
  193. {M10V_PLL11, NULL, 2, 75, -1},
  194. };
  195. static const struct m10v_clk_div_fixed_data m10v_div_fixed_data[] = {
  196. {"usb2", NULL, 2, 1, -1},
  197. {"pcisuppclk", NULL, 20, 1, -1},
  198. {M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1},
  199. {M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1},
  200. {M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1},
  201. {M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1},
  202. {M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1},
  203. {M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1},
  204. {"ca7wd", M10V_PLL2DIV2, 12, 1, -1},
  205. {"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1},
  206. {M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1},
  207. {M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1},
  208. {M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1},
  209. {M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1},
  210. {M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1},
  211. {M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1},
  212. {M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1},
  213. {M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1},
  214. {M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1},
  215. {M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1},
  216. {M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1},
  217. {M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1},
  218. {M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1},
  219. {M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1},
  220. };
  221. static const struct m10v_clk_div_factors m10v_div_factor_data[] = {
  222. {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
  223. M10V_EMMCCLK_ID},
  224. {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
  225. {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
  226. {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
  227. {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
  228. {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
  229. {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
  230. {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
  231. {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
  232. {"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID},
  233. {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
  234. {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
  235. };
  236. static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
  237. {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
  238. CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
  239. {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
  240. CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID},
  241. {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
  242. CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
  243. {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
  244. CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
  245. };
  246. static u8 m10v_mux_get_parent(struct clk_hw *hw)
  247. {
  248. struct clk_mux *mux = to_clk_mux(hw);
  249. u32 val;
  250. val = readl(mux->reg) >> mux->shift;
  251. val &= mux->mask;
  252. return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
  253. }
  254. static int m10v_mux_set_parent(struct clk_hw *hw, u8 index)
  255. {
  256. struct clk_mux *mux = to_clk_mux(hw);
  257. u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
  258. unsigned long flags = 0;
  259. u32 reg;
  260. u32 write_en = BIT(fls(mux->mask) - 1);
  261. if (mux->lock)
  262. spin_lock_irqsave(mux->lock, flags);
  263. else
  264. __acquire(mux->lock);
  265. reg = readl(mux->reg);
  266. reg &= ~(mux->mask << mux->shift);
  267. val = (val | write_en) << mux->shift;
  268. reg |= val;
  269. writel(reg, mux->reg);
  270. if (mux->lock)
  271. spin_unlock_irqrestore(mux->lock, flags);
  272. else
  273. __release(mux->lock);
  274. return 0;
  275. }
  276. static const struct clk_ops m10v_mux_ops = {
  277. .get_parent = m10v_mux_get_parent,
  278. .set_parent = m10v_mux_set_parent,
  279. .determine_rate = __clk_mux_determine_rate,
  280. };
  281. static struct clk_hw *m10v_clk_hw_register_mux(struct device *dev,
  282. const char *name, const char * const *parent_names,
  283. u8 num_parents, unsigned long flags, void __iomem *reg,
  284. u8 shift, u32 mask, u8 clk_mux_flags, u32 *table,
  285. spinlock_t *lock)
  286. {
  287. struct clk_mux *mux;
  288. struct clk_hw *hw;
  289. struct clk_init_data init;
  290. int ret;
  291. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  292. if (!mux)
  293. return ERR_PTR(-ENOMEM);
  294. init.name = name;
  295. init.ops = &m10v_mux_ops;
  296. init.flags = flags;
  297. init.parent_names = parent_names;
  298. init.num_parents = num_parents;
  299. mux->reg = reg;
  300. mux->shift = shift;
  301. mux->mask = mask;
  302. mux->flags = clk_mux_flags;
  303. mux->lock = lock;
  304. mux->table = table;
  305. mux->hw.init = &init;
  306. hw = &mux->hw;
  307. ret = clk_hw_register(dev, hw);
  308. if (ret) {
  309. kfree(mux);
  310. hw = ERR_PTR(ret);
  311. }
  312. return hw;
  313. }
  314. struct m10v_clk_divider {
  315. struct clk_hw hw;
  316. void __iomem *reg;
  317. u8 shift;
  318. u8 width;
  319. u8 flags;
  320. const struct clk_div_table *table;
  321. spinlock_t *lock;
  322. void __iomem *write_valid_reg;
  323. };
  324. static unsigned long m10v_clk_divider_recalc_rate(struct clk_hw *hw,
  325. unsigned long parent_rate)
  326. {
  327. struct m10v_clk_divider *divider = to_m10v_div(hw);
  328. unsigned int val;
  329. val = readl(divider->reg) >> divider->shift;
  330. val &= clk_div_mask(divider->width);
  331. return divider_recalc_rate(hw, parent_rate, val, divider->table,
  332. divider->flags, divider->width);
  333. }
  334. static long m10v_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
  335. unsigned long *prate)
  336. {
  337. struct m10v_clk_divider *divider = to_m10v_div(hw);
  338. /* if read only, just return current value */
  339. if (divider->flags & CLK_DIVIDER_READ_ONLY) {
  340. u32 val;
  341. val = readl(divider->reg) >> divider->shift;
  342. val &= clk_div_mask(divider->width);
  343. return divider_ro_round_rate(hw, rate, prate, divider->table,
  344. divider->width, divider->flags,
  345. val);
  346. }
  347. return divider_round_rate(hw, rate, prate, divider->table,
  348. divider->width, divider->flags);
  349. }
  350. static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
  351. unsigned long parent_rate)
  352. {
  353. struct m10v_clk_divider *divider = to_m10v_div(hw);
  354. int value;
  355. unsigned long flags = 0;
  356. u32 val;
  357. u32 write_en = BIT(divider->width - 1);
  358. value = divider_get_val(rate, parent_rate, divider->table,
  359. divider->width, divider->flags);
  360. if (value < 0)
  361. return value;
  362. if (divider->lock)
  363. spin_lock_irqsave(divider->lock, flags);
  364. else
  365. __acquire(divider->lock);
  366. val = readl(divider->reg);
  367. val &= ~(clk_div_mask(divider->width) << divider->shift);
  368. val |= ((u32)value | write_en) << divider->shift;
  369. writel(val, divider->reg);
  370. if (divider->write_valid_reg) {
  371. writel(M10V_DCHREQ, divider->write_valid_reg);
  372. if (readl_poll_timeout(divider->write_valid_reg, val,
  373. !val, M10V_UPOLL_RATE, M10V_UTIMEOUT))
  374. pr_err("%s:%s couldn't stabilize\n",
  375. __func__, clk_hw_get_name(hw));
  376. }
  377. if (divider->lock)
  378. spin_unlock_irqrestore(divider->lock, flags);
  379. else
  380. __release(divider->lock);
  381. return 0;
  382. }
  383. static const struct clk_ops m10v_clk_divider_ops = {
  384. .recalc_rate = m10v_clk_divider_recalc_rate,
  385. .round_rate = m10v_clk_divider_round_rate,
  386. .set_rate = m10v_clk_divider_set_rate,
  387. };
  388. static struct clk_hw *m10v_clk_hw_register_divider(struct device *dev,
  389. const char *name, const char *parent_name, unsigned long flags,
  390. void __iomem *reg, u8 shift, u8 width,
  391. u8 clk_divider_flags, const struct clk_div_table *table,
  392. spinlock_t *lock, void __iomem *write_valid_reg)
  393. {
  394. struct m10v_clk_divider *div;
  395. struct clk_hw *hw;
  396. struct clk_init_data init;
  397. int ret;
  398. div = kzalloc(sizeof(*div), GFP_KERNEL);
  399. if (!div)
  400. return ERR_PTR(-ENOMEM);
  401. init.name = name;
  402. init.ops = &m10v_clk_divider_ops;
  403. init.flags = flags;
  404. init.parent_names = &parent_name;
  405. init.num_parents = 1;
  406. div->reg = reg;
  407. div->shift = shift;
  408. div->width = width;
  409. div->flags = clk_divider_flags;
  410. div->lock = lock;
  411. div->hw.init = &init;
  412. div->table = table;
  413. div->write_valid_reg = write_valid_reg;
  414. /* register the clock */
  415. hw = &div->hw;
  416. ret = clk_hw_register(dev, hw);
  417. if (ret) {
  418. kfree(div);
  419. hw = ERR_PTR(ret);
  420. }
  421. return hw;
  422. }
  423. static void m10v_reg_div_pre(const struct m10v_clk_div_factors *factors,
  424. struct clk_hw_onecell_data *clk_data,
  425. void __iomem *base)
  426. {
  427. struct clk_hw *hw;
  428. void __iomem *write_valid_reg;
  429. /*
  430. * The registers on CLKSEL(9) or CLKSEL(10) need additional
  431. * writing to become valid.
  432. */
  433. if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10)))
  434. write_valid_reg = base + CLKSEL(11);
  435. else
  436. write_valid_reg = NULL;
  437. hw = m10v_clk_hw_register_divider(NULL, factors->name,
  438. factors->parent_name,
  439. CLK_SET_RATE_PARENT,
  440. base + factors->offset,
  441. factors->shift,
  442. factors->width, factors->div_flags,
  443. factors->table,
  444. &m10v_crglock, write_valid_reg);
  445. if (factors->onecell_idx >= 0)
  446. clk_data->hws[factors->onecell_idx] = hw;
  447. }
  448. static void m10v_reg_fixed_pre(const struct m10v_clk_div_fixed_data *factors,
  449. struct clk_hw_onecell_data *clk_data,
  450. const char *parent_name)
  451. {
  452. struct clk_hw *hw;
  453. const char *pn = factors->parent_name ?
  454. factors->parent_name : parent_name;
  455. hw = clk_hw_register_fixed_factor(NULL, factors->name, pn, 0,
  456. factors->mult, factors->div);
  457. if (factors->onecell_idx >= 0)
  458. clk_data->hws[factors->onecell_idx] = hw;
  459. }
  460. static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors,
  461. struct clk_hw_onecell_data *clk_data,
  462. void __iomem *base)
  463. {
  464. struct clk_hw *hw;
  465. hw = m10v_clk_hw_register_mux(NULL, factors->name,
  466. factors->parent_names,
  467. factors->num_parents,
  468. CLK_SET_RATE_PARENT,
  469. base + factors->offset, factors->shift,
  470. factors->mask, factors->mux_flags,
  471. factors->table, &m10v_crglock);
  472. if (factors->onecell_idx >= 0)
  473. clk_data->hws[factors->onecell_idx] = hw;
  474. }
  475. static int m10v_clk_probe(struct platform_device *pdev)
  476. {
  477. int id;
  478. struct resource *res;
  479. struct device *dev = &pdev->dev;
  480. struct device_node *np = dev->of_node;
  481. void __iomem *base;
  482. const char *parent_name;
  483. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  484. base = devm_ioremap_resource(dev, res);
  485. if (IS_ERR(base))
  486. return PTR_ERR(base);
  487. parent_name = of_clk_get_parent_name(np, 0);
  488. for (id = 0; id < ARRAY_SIZE(m10v_div_factor_data); ++id)
  489. m10v_reg_div_pre(&m10v_div_factor_data[id],
  490. m10v_clk_data, base);
  491. for (id = 0; id < ARRAY_SIZE(m10v_div_fixed_data); ++id)
  492. m10v_reg_fixed_pre(&m10v_div_fixed_data[id],
  493. m10v_clk_data, parent_name);
  494. for (id = 0; id < ARRAY_SIZE(m10v_mux_factor_data); ++id)
  495. m10v_reg_mux_pre(&m10v_mux_factor_data[id],
  496. m10v_clk_data, base);
  497. for (id = 0; id < M10V_NUM_CLKS; id++) {
  498. if (IS_ERR(m10v_clk_data->hws[id]))
  499. return PTR_ERR(m10v_clk_data->hws[id]);
  500. }
  501. return 0;
  502. }
  503. static const struct of_device_id m10v_clk_dt_ids[] = {
  504. { .compatible = "socionext,milbeaut-m10v-ccu", },
  505. { }
  506. };
  507. static struct platform_driver m10v_clk_driver = {
  508. .probe = m10v_clk_probe,
  509. .driver = {
  510. .name = "m10v-ccu",
  511. .of_match_table = m10v_clk_dt_ids,
  512. },
  513. };
  514. builtin_platform_driver(m10v_clk_driver);
  515. static void __init m10v_cc_init(struct device_node *np)
  516. {
  517. int id;
  518. void __iomem *base;
  519. const char *parent_name;
  520. struct clk_hw *hw;
  521. m10v_clk_data = kzalloc(struct_size(m10v_clk_data, hws,
  522. M10V_NUM_CLKS),
  523. GFP_KERNEL);
  524. if (!m10v_clk_data)
  525. return;
  526. base = of_iomap(np, 0);
  527. if (!base) {
  528. kfree(m10v_clk_data);
  529. return;
  530. }
  531. parent_name = of_clk_get_parent_name(np, 0);
  532. if (!parent_name) {
  533. kfree(m10v_clk_data);
  534. iounmap(base);
  535. return;
  536. }
  537. /*
  538. * This way all clocks fetched before the platform device probes,
  539. * except those we assign here for early use, will be deferred.
  540. */
  541. for (id = 0; id < M10V_NUM_CLKS; id++)
  542. m10v_clk_data->hws[id] = ERR_PTR(-EPROBE_DEFER);
  543. /*
  544. * PLLs are set by bootloader so this driver registers them as the
  545. * fixed factor.
  546. */
  547. for (id = 0; id < ARRAY_SIZE(m10v_pll_fixed_data); ++id)
  548. m10v_reg_fixed_pre(&m10v_pll_fixed_data[id],
  549. m10v_clk_data, parent_name);
  550. /*
  551. * timer consumes "rclk" so it needs to register here.
  552. */
  553. hw = m10v_clk_hw_register_divider(NULL, "rclk", M10V_PLL10DIV2, 0,
  554. base + CLKSEL(1), 0, 3, 0, rclk_table,
  555. &m10v_crglock, NULL);
  556. m10v_clk_data->hws[M10V_RCLK_ID] = hw;
  557. m10v_clk_data->num = M10V_NUM_CLKS;
  558. of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data);
  559. }
  560. CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);