clk-lochnagar.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Lochnagar clock control
  4. *
  5. * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
  6. * Cirrus Logic International Semiconductor Ltd.
  7. *
  8. * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/device.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. #include <linux/mfd/lochnagar1_regs.h>
  18. #include <linux/mfd/lochnagar2_regs.h>
  19. #include <dt-bindings/clk/lochnagar.h>
  20. #define LOCHNAGAR_NUM_CLOCKS (LOCHNAGAR_SPDIF_CLKOUT + 1)
  21. struct lochnagar_clk {
  22. const char * const name;
  23. struct clk_hw hw;
  24. struct lochnagar_clk_priv *priv;
  25. u16 cfg_reg;
  26. u16 ena_mask;
  27. u16 src_reg;
  28. u16 src_mask;
  29. };
  30. struct lochnagar_clk_priv {
  31. struct device *dev;
  32. struct regmap *regmap;
  33. struct lochnagar_clk lclks[LOCHNAGAR_NUM_CLOCKS];
  34. };
  35. #define LN_PARENT(NAME) { .name = NAME, .fw_name = NAME }
  36. static const struct clk_parent_data lochnagar1_clk_parents[] = {
  37. LN_PARENT("ln-none"),
  38. LN_PARENT("ln-spdif-mclk"),
  39. LN_PARENT("ln-psia1-mclk"),
  40. LN_PARENT("ln-psia2-mclk"),
  41. LN_PARENT("ln-cdc-clkout"),
  42. LN_PARENT("ln-dsp-clkout"),
  43. LN_PARENT("ln-pmic-32k"),
  44. LN_PARENT("ln-gf-mclk1"),
  45. LN_PARENT("ln-gf-mclk3"),
  46. LN_PARENT("ln-gf-mclk2"),
  47. LN_PARENT("ln-gf-mclk4"),
  48. };
  49. static const struct clk_parent_data lochnagar2_clk_parents[] = {
  50. LN_PARENT("ln-none"),
  51. LN_PARENT("ln-cdc-clkout"),
  52. LN_PARENT("ln-dsp-clkout"),
  53. LN_PARENT("ln-pmic-32k"),
  54. LN_PARENT("ln-spdif-mclk"),
  55. LN_PARENT("ln-clk-12m"),
  56. LN_PARENT("ln-clk-11m"),
  57. LN_PARENT("ln-clk-24m"),
  58. LN_PARENT("ln-clk-22m"),
  59. LN_PARENT("ln-clk-8m"),
  60. LN_PARENT("ln-usb-clk-24m"),
  61. LN_PARENT("ln-gf-mclk1"),
  62. LN_PARENT("ln-gf-mclk3"),
  63. LN_PARENT("ln-gf-mclk2"),
  64. LN_PARENT("ln-psia1-mclk"),
  65. LN_PARENT("ln-psia2-mclk"),
  66. LN_PARENT("ln-spdif-clkout"),
  67. LN_PARENT("ln-adat-mclk"),
  68. LN_PARENT("ln-usb-clk-12m"),
  69. };
  70. #define LN1_CLK(ID, NAME, REG) \
  71. [LOCHNAGAR_##ID] = { \
  72. .name = NAME, \
  73. .cfg_reg = LOCHNAGAR1_##REG, \
  74. .ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
  75. .src_reg = LOCHNAGAR1_##ID##_SEL, \
  76. .src_mask = LOCHNAGAR1_SRC_MASK, \
  77. }
  78. #define LN2_CLK(ID, NAME) \
  79. [LOCHNAGAR_##ID] = { \
  80. .name = NAME, \
  81. .cfg_reg = LOCHNAGAR2_##ID##_CTRL, \
  82. .src_reg = LOCHNAGAR2_##ID##_CTRL, \
  83. .ena_mask = LOCHNAGAR2_CLK_ENA_MASK, \
  84. .src_mask = LOCHNAGAR2_CLK_SRC_MASK, \
  85. }
  86. static const struct lochnagar_clk lochnagar1_clks[LOCHNAGAR_NUM_CLOCKS] = {
  87. LN1_CLK(CDC_MCLK1, "ln-cdc-mclk1", CDC_AIF_CTRL2),
  88. LN1_CLK(CDC_MCLK2, "ln-cdc-mclk2", CDC_AIF_CTRL2),
  89. LN1_CLK(DSP_CLKIN, "ln-dsp-clkin", DSP_AIF),
  90. LN1_CLK(GF_CLKOUT1, "ln-gf-clkout1", GF_AIF1),
  91. };
  92. static const struct lochnagar_clk lochnagar2_clks[LOCHNAGAR_NUM_CLOCKS] = {
  93. LN2_CLK(CDC_MCLK1, "ln-cdc-mclk1"),
  94. LN2_CLK(CDC_MCLK2, "ln-cdc-mclk2"),
  95. LN2_CLK(DSP_CLKIN, "ln-dsp-clkin"),
  96. LN2_CLK(GF_CLKOUT1, "ln-gf-clkout1"),
  97. LN2_CLK(GF_CLKOUT2, "ln-gf-clkout2"),
  98. LN2_CLK(PSIA1_MCLK, "ln-psia1-mclk"),
  99. LN2_CLK(PSIA2_MCLK, "ln-psia2-mclk"),
  100. LN2_CLK(SPDIF_MCLK, "ln-spdif-mclk"),
  101. LN2_CLK(ADAT_MCLK, "ln-adat-mclk"),
  102. LN2_CLK(SOUNDCARD_MCLK, "ln-soundcard-mclk"),
  103. };
  104. struct lochnagar_config {
  105. const struct clk_parent_data *parents;
  106. int nparents;
  107. const struct lochnagar_clk *clks;
  108. };
  109. static const struct lochnagar_config lochnagar1_conf = {
  110. .parents = lochnagar1_clk_parents,
  111. .nparents = ARRAY_SIZE(lochnagar1_clk_parents),
  112. .clks = lochnagar1_clks,
  113. };
  114. static const struct lochnagar_config lochnagar2_conf = {
  115. .parents = lochnagar2_clk_parents,
  116. .nparents = ARRAY_SIZE(lochnagar2_clk_parents),
  117. .clks = lochnagar2_clks,
  118. };
  119. static inline struct lochnagar_clk *lochnagar_hw_to_lclk(struct clk_hw *hw)
  120. {
  121. return container_of(hw, struct lochnagar_clk, hw);
  122. }
  123. static int lochnagar_clk_prepare(struct clk_hw *hw)
  124. {
  125. struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
  126. struct lochnagar_clk_priv *priv = lclk->priv;
  127. struct regmap *regmap = priv->regmap;
  128. int ret;
  129. ret = regmap_update_bits(regmap, lclk->cfg_reg,
  130. lclk->ena_mask, lclk->ena_mask);
  131. if (ret < 0)
  132. dev_dbg(priv->dev, "Failed to prepare %s: %d\n",
  133. lclk->name, ret);
  134. return ret;
  135. }
  136. static void lochnagar_clk_unprepare(struct clk_hw *hw)
  137. {
  138. struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
  139. struct lochnagar_clk_priv *priv = lclk->priv;
  140. struct regmap *regmap = priv->regmap;
  141. int ret;
  142. ret = regmap_update_bits(regmap, lclk->cfg_reg, lclk->ena_mask, 0);
  143. if (ret < 0)
  144. dev_dbg(priv->dev, "Failed to unprepare %s: %d\n",
  145. lclk->name, ret);
  146. }
  147. static int lochnagar_clk_set_parent(struct clk_hw *hw, u8 index)
  148. {
  149. struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
  150. struct lochnagar_clk_priv *priv = lclk->priv;
  151. struct regmap *regmap = priv->regmap;
  152. int ret;
  153. ret = regmap_update_bits(regmap, lclk->src_reg, lclk->src_mask, index);
  154. if (ret < 0)
  155. dev_dbg(priv->dev, "Failed to reparent %s: %d\n",
  156. lclk->name, ret);
  157. return ret;
  158. }
  159. static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
  160. {
  161. struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
  162. struct lochnagar_clk_priv *priv = lclk->priv;
  163. struct regmap *regmap = priv->regmap;
  164. unsigned int val;
  165. int ret;
  166. ret = regmap_read(regmap, lclk->src_reg, &val);
  167. if (ret < 0) {
  168. dev_dbg(priv->dev, "Failed to read parent of %s: %d\n",
  169. lclk->name, ret);
  170. return clk_hw_get_num_parents(hw);
  171. }
  172. val &= lclk->src_mask;
  173. return val;
  174. }
  175. static const struct clk_ops lochnagar_clk_ops = {
  176. .prepare = lochnagar_clk_prepare,
  177. .unprepare = lochnagar_clk_unprepare,
  178. .set_parent = lochnagar_clk_set_parent,
  179. .get_parent = lochnagar_clk_get_parent,
  180. };
  181. static struct clk_hw *
  182. lochnagar_of_clk_hw_get(struct of_phandle_args *clkspec, void *data)
  183. {
  184. struct lochnagar_clk_priv *priv = data;
  185. unsigned int idx = clkspec->args[0];
  186. if (idx >= ARRAY_SIZE(priv->lclks)) {
  187. dev_err(priv->dev, "Invalid index %u\n", idx);
  188. return ERR_PTR(-EINVAL);
  189. }
  190. return &priv->lclks[idx].hw;
  191. }
  192. static const struct of_device_id lochnagar_of_match[] = {
  193. { .compatible = "cirrus,lochnagar1-clk", .data = &lochnagar1_conf },
  194. { .compatible = "cirrus,lochnagar2-clk", .data = &lochnagar2_conf },
  195. {}
  196. };
  197. MODULE_DEVICE_TABLE(of, lochnagar_of_match);
  198. static int lochnagar_clk_probe(struct platform_device *pdev)
  199. {
  200. struct clk_init_data clk_init = {
  201. .ops = &lochnagar_clk_ops,
  202. };
  203. struct device *dev = &pdev->dev;
  204. struct lochnagar_clk_priv *priv;
  205. const struct of_device_id *of_id;
  206. struct lochnagar_clk *lclk;
  207. struct lochnagar_config *conf;
  208. int ret, i;
  209. of_id = of_match_device(lochnagar_of_match, dev);
  210. if (!of_id)
  211. return -EINVAL;
  212. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  213. if (!priv)
  214. return -ENOMEM;
  215. priv->dev = dev;
  216. priv->regmap = dev_get_regmap(dev->parent, NULL);
  217. conf = (struct lochnagar_config *)of_id->data;
  218. memcpy(priv->lclks, conf->clks, sizeof(priv->lclks));
  219. clk_init.parent_data = conf->parents;
  220. clk_init.num_parents = conf->nparents;
  221. for (i = 0; i < ARRAY_SIZE(priv->lclks); i++) {
  222. lclk = &priv->lclks[i];
  223. if (!lclk->name)
  224. continue;
  225. clk_init.name = lclk->name;
  226. lclk->priv = priv;
  227. lclk->hw.init = &clk_init;
  228. ret = devm_clk_hw_register(dev, &lclk->hw);
  229. if (ret) {
  230. dev_err(dev, "Failed to register %s: %d\n",
  231. lclk->name, ret);
  232. return ret;
  233. }
  234. }
  235. ret = devm_of_clk_add_hw_provider(dev, lochnagar_of_clk_hw_get, priv);
  236. if (ret < 0)
  237. dev_err(dev, "Failed to register provider: %d\n", ret);
  238. return ret;
  239. }
  240. static struct platform_driver lochnagar_clk_driver = {
  241. .driver = {
  242. .name = "lochnagar-clk",
  243. .of_match_table = lochnagar_of_match,
  244. },
  245. .probe = lochnagar_clk_probe,
  246. };
  247. module_platform_driver(lochnagar_clk_driver);
  248. MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
  249. MODULE_DESCRIPTION("Clock driver for Cirrus Logic Lochnagar Board");
  250. MODULE_LICENSE("GPL v2");