clk-gemini.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Cortina Gemini SoC Clock Controller driver
  4. * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
  5. */
  6. #define pr_fmt(fmt) "clk-gemini: " fmt
  7. #include <linux/init.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/regmap.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/reset-controller.h>
  20. #include <dt-bindings/reset/cortina,gemini-reset.h>
  21. #include <dt-bindings/clock/cortina,gemini-clock.h>
  22. /* Globally visible clocks */
  23. static DEFINE_SPINLOCK(gemini_clk_lock);
  24. #define GEMINI_GLOBAL_STATUS 0x04
  25. #define PLL_OSC_SEL BIT(30)
  26. #define AHBSPEED_SHIFT (15)
  27. #define AHBSPEED_MASK 0x07
  28. #define CPU_AHB_RATIO_SHIFT (18)
  29. #define CPU_AHB_RATIO_MASK 0x03
  30. #define GEMINI_GLOBAL_PLL_CONTROL 0x08
  31. #define GEMINI_GLOBAL_SOFT_RESET 0x0c
  32. #define GEMINI_GLOBAL_MISC_CONTROL 0x30
  33. #define PCI_CLK_66MHZ BIT(18)
  34. #define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
  35. #define PCI_CLKRUN_EN BIT(16)
  36. #define TVC_HALFDIV_SHIFT (24)
  37. #define TVC_HALFDIV_MASK 0x1f
  38. #define SECURITY_CLK_SEL BIT(29)
  39. #define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44
  40. #define PCI_DLL_BYPASS BIT(31)
  41. #define PCI_DLL_TAP_SEL_MASK 0x1f
  42. /**
  43. * struct gemini_data_data - Gemini gated clocks
  44. * @bit_idx: the bit used to gate this clock in the clock register
  45. * @name: the clock name
  46. * @parent_name: the name of the parent clock
  47. * @flags: standard clock framework flags
  48. */
  49. struct gemini_gate_data {
  50. u8 bit_idx;
  51. const char *name;
  52. const char *parent_name;
  53. unsigned long flags;
  54. };
  55. /**
  56. * struct clk_gemini_pci - Gemini PCI clock
  57. * @hw: corresponding clock hardware entry
  58. * @map: regmap to access the registers
  59. * @rate: current rate
  60. */
  61. struct clk_gemini_pci {
  62. struct clk_hw hw;
  63. struct regmap *map;
  64. unsigned long rate;
  65. };
  66. /**
  67. * struct gemini_reset - gemini reset controller
  68. * @map: regmap to access the containing system controller
  69. * @rcdev: reset controller device
  70. */
  71. struct gemini_reset {
  72. struct regmap *map;
  73. struct reset_controller_dev rcdev;
  74. };
  75. /* Keeps track of all clocks */
  76. static struct clk_hw_onecell_data *gemini_clk_data;
  77. static const struct gemini_gate_data gemini_gates[] = {
  78. { 1, "security-gate", "secdiv", 0 },
  79. { 2, "gmac0-gate", "ahb", 0 },
  80. { 3, "gmac1-gate", "ahb", 0 },
  81. { 4, "sata0-gate", "ahb", 0 },
  82. { 5, "sata1-gate", "ahb", 0 },
  83. { 6, "usb0-gate", "ahb", 0 },
  84. { 7, "usb1-gate", "ahb", 0 },
  85. { 8, "ide-gate", "ahb", 0 },
  86. { 9, "pci-gate", "ahb", 0 },
  87. /*
  88. * The DDR controller may never have a driver, but certainly must
  89. * not be gated off.
  90. */
  91. { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
  92. /*
  93. * The flash controller must be on to access NOR flash through the
  94. * memory map.
  95. */
  96. { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
  97. { 12, "tvc-gate", "ahb", 0 },
  98. { 13, "boot-gate", "apb", 0 },
  99. };
  100. #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
  101. #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
  102. static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
  103. unsigned long parent_rate)
  104. {
  105. struct clk_gemini_pci *pciclk = to_pciclk(hw);
  106. u32 val;
  107. regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
  108. if (val & PCI_CLK_66MHZ)
  109. return 66000000;
  110. return 33000000;
  111. }
  112. static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
  113. unsigned long *prate)
  114. {
  115. /* We support 33 and 66 MHz */
  116. if (rate < 48000000)
  117. return 33000000;
  118. return 66000000;
  119. }
  120. static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
  121. unsigned long parent_rate)
  122. {
  123. struct clk_gemini_pci *pciclk = to_pciclk(hw);
  124. if (rate == 33000000)
  125. return regmap_update_bits(pciclk->map,
  126. GEMINI_GLOBAL_MISC_CONTROL,
  127. PCI_CLK_66MHZ, 0);
  128. if (rate == 66000000)
  129. return regmap_update_bits(pciclk->map,
  130. GEMINI_GLOBAL_MISC_CONTROL,
  131. 0, PCI_CLK_66MHZ);
  132. return -EINVAL;
  133. }
  134. static int gemini_pci_enable(struct clk_hw *hw)
  135. {
  136. struct clk_gemini_pci *pciclk = to_pciclk(hw);
  137. regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
  138. 0, PCI_CLKRUN_EN);
  139. return 0;
  140. }
  141. static void gemini_pci_disable(struct clk_hw *hw)
  142. {
  143. struct clk_gemini_pci *pciclk = to_pciclk(hw);
  144. regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
  145. PCI_CLKRUN_EN, 0);
  146. }
  147. static int gemini_pci_is_enabled(struct clk_hw *hw)
  148. {
  149. struct clk_gemini_pci *pciclk = to_pciclk(hw);
  150. unsigned int val;
  151. regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
  152. return !!(val & PCI_CLKRUN_EN);
  153. }
  154. static const struct clk_ops gemini_pci_clk_ops = {
  155. .recalc_rate = gemini_pci_recalc_rate,
  156. .round_rate = gemini_pci_round_rate,
  157. .set_rate = gemini_pci_set_rate,
  158. .enable = gemini_pci_enable,
  159. .disable = gemini_pci_disable,
  160. .is_enabled = gemini_pci_is_enabled,
  161. };
  162. static struct clk_hw *gemini_pci_clk_setup(const char *name,
  163. const char *parent_name,
  164. struct regmap *map)
  165. {
  166. struct clk_gemini_pci *pciclk;
  167. struct clk_init_data init;
  168. int ret;
  169. pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
  170. if (!pciclk)
  171. return ERR_PTR(-ENOMEM);
  172. init.name = name;
  173. init.ops = &gemini_pci_clk_ops;
  174. init.flags = 0;
  175. init.parent_names = &parent_name;
  176. init.num_parents = 1;
  177. pciclk->map = map;
  178. pciclk->hw.init = &init;
  179. ret = clk_hw_register(NULL, &pciclk->hw);
  180. if (ret) {
  181. kfree(pciclk);
  182. return ERR_PTR(ret);
  183. }
  184. return &pciclk->hw;
  185. }
  186. /*
  187. * This is a self-deasserting reset controller.
  188. */
  189. static int gemini_reset(struct reset_controller_dev *rcdev,
  190. unsigned long id)
  191. {
  192. struct gemini_reset *gr = to_gemini_reset(rcdev);
  193. /* Manual says to always set BIT 30 (CPU1) to 1 */
  194. return regmap_write(gr->map,
  195. GEMINI_GLOBAL_SOFT_RESET,
  196. BIT(GEMINI_RESET_CPU1) | BIT(id));
  197. }
  198. static int gemini_reset_assert(struct reset_controller_dev *rcdev,
  199. unsigned long id)
  200. {
  201. return 0;
  202. }
  203. static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
  204. unsigned long id)
  205. {
  206. return 0;
  207. }
  208. static int gemini_reset_status(struct reset_controller_dev *rcdev,
  209. unsigned long id)
  210. {
  211. struct gemini_reset *gr = to_gemini_reset(rcdev);
  212. u32 val;
  213. int ret;
  214. ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
  215. if (ret)
  216. return ret;
  217. return !!(val & BIT(id));
  218. }
  219. static const struct reset_control_ops gemini_reset_ops = {
  220. .reset = gemini_reset,
  221. .assert = gemini_reset_assert,
  222. .deassert = gemini_reset_deassert,
  223. .status = gemini_reset_status,
  224. };
  225. static int gemini_clk_probe(struct platform_device *pdev)
  226. {
  227. /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
  228. unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
  229. unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
  230. void __iomem *base;
  231. struct gemini_reset *gr;
  232. struct regmap *map;
  233. struct clk_hw *hw;
  234. struct device *dev = &pdev->dev;
  235. struct device_node *np = dev->of_node;
  236. unsigned int mult, div;
  237. struct resource *res;
  238. u32 val;
  239. int ret;
  240. int i;
  241. gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
  242. if (!gr)
  243. return -ENOMEM;
  244. /* Remap the system controller for the exclusive register */
  245. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  246. base = devm_ioremap_resource(dev, res);
  247. if (IS_ERR(base))
  248. return PTR_ERR(base);
  249. map = syscon_node_to_regmap(np);
  250. if (IS_ERR(map)) {
  251. dev_err(dev, "no syscon regmap\n");
  252. return PTR_ERR(map);
  253. }
  254. gr->map = map;
  255. gr->rcdev.owner = THIS_MODULE;
  256. gr->rcdev.nr_resets = 32;
  257. gr->rcdev.ops = &gemini_reset_ops;
  258. gr->rcdev.of_node = np;
  259. ret = devm_reset_controller_register(dev, &gr->rcdev);
  260. if (ret) {
  261. dev_err(dev, "could not register reset controller\n");
  262. return ret;
  263. }
  264. /* RTC clock 32768 Hz */
  265. hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
  266. gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
  267. /* CPU clock derived as a fixed ratio from the AHB clock */
  268. regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
  269. val >>= CPU_AHB_RATIO_SHIFT;
  270. val &= CPU_AHB_RATIO_MASK;
  271. hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
  272. cpu_ahb_mult[val],
  273. cpu_ahb_div[val]);
  274. gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
  275. /* Security clock is 1:1 or 0.75 of APB */
  276. regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
  277. if (val & SECURITY_CLK_SEL) {
  278. mult = 1;
  279. div = 1;
  280. } else {
  281. mult = 3;
  282. div = 4;
  283. }
  284. hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
  285. /*
  286. * These are the leaf gates, at boot no clocks are gated.
  287. */
  288. for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
  289. const struct gemini_gate_data *gd;
  290. gd = &gemini_gates[i];
  291. gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
  292. clk_hw_register_gate(NULL, gd->name,
  293. gd->parent_name,
  294. gd->flags,
  295. base + GEMINI_GLOBAL_CLOCK_CONTROL,
  296. gd->bit_idx,
  297. CLK_GATE_SET_TO_DISABLE,
  298. &gemini_clk_lock);
  299. }
  300. /*
  301. * The TV Interface Controller has a 5-bit half divider register.
  302. * This clock is supposed to be 27MHz as this is an exact multiple
  303. * of PAL and NTSC frequencies. The register is undocumented :(
  304. * FIXME: figure out the parent and how the divider works.
  305. */
  306. mult = 1;
  307. div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
  308. dev_dbg(dev, "TVC half divider value = %d\n", div);
  309. div += 1;
  310. hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
  311. gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
  312. /* FIXME: very unclear what the parent is */
  313. hw = gemini_pci_clk_setup("PCI", "xtal", map);
  314. gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
  315. /* FIXME: very unclear what the parent is */
  316. hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
  317. gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
  318. return 0;
  319. }
  320. static const struct of_device_id gemini_clk_dt_ids[] = {
  321. { .compatible = "cortina,gemini-syscon", },
  322. { /* sentinel */ },
  323. };
  324. static struct platform_driver gemini_clk_driver = {
  325. .probe = gemini_clk_probe,
  326. .driver = {
  327. .name = "gemini-clk",
  328. .of_match_table = gemini_clk_dt_ids,
  329. .suppress_bind_attrs = true,
  330. },
  331. };
  332. builtin_platform_driver(gemini_clk_driver);
  333. static void __init gemini_cc_init(struct device_node *np)
  334. {
  335. struct regmap *map;
  336. struct clk_hw *hw;
  337. unsigned long freq;
  338. unsigned int mult, div;
  339. u32 val;
  340. int ret;
  341. int i;
  342. gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws,
  343. GEMINI_NUM_CLKS),
  344. GFP_KERNEL);
  345. if (!gemini_clk_data)
  346. return;
  347. /*
  348. * This way all clock fetched before the platform device probes,
  349. * except those we assign here for early use, will be deferred.
  350. */
  351. for (i = 0; i < GEMINI_NUM_CLKS; i++)
  352. gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
  353. map = syscon_node_to_regmap(np);
  354. if (IS_ERR(map)) {
  355. pr_err("no syscon regmap\n");
  356. return;
  357. }
  358. /*
  359. * We check that the regmap works on this very first access,
  360. * but as this is an MMIO-backed regmap, subsequent regmap
  361. * access is not going to fail and we skip error checks from
  362. * this point.
  363. */
  364. ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
  365. if (ret) {
  366. pr_err("failed to read global status register\n");
  367. return;
  368. }
  369. /*
  370. * XTAL is the crystal oscillator, 60 or 30 MHz selected from
  371. * strap pin E6
  372. */
  373. if (val & PLL_OSC_SEL)
  374. freq = 30000000;
  375. else
  376. freq = 60000000;
  377. hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
  378. pr_debug("main crystal @%lu MHz\n", freq / 1000000);
  379. /* VCO clock derived from the crystal */
  380. mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
  381. div = 2;
  382. /* If we run on 30 MHz crystal we have to multiply with two */
  383. if (val & PLL_OSC_SEL)
  384. mult *= 2;
  385. hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
  386. /* The AHB clock is always 1/3 of the VCO */
  387. hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
  388. gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
  389. /* The APB clock is always 1/6 of the AHB */
  390. hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
  391. gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
  392. /* Register the clocks to be accessed by the device tree */
  393. gemini_clk_data->num = GEMINI_NUM_CLKS;
  394. of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
  395. }
  396. CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);