clk-gate.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
  4. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  5. *
  6. * Gated clock implementation
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/module.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <linux/string.h>
  14. /**
  15. * DOC: basic gatable clock which can gate and ungate it's ouput
  16. *
  17. * Traits of this clock:
  18. * prepare - clk_(un)prepare only ensures parent is (un)prepared
  19. * enable - clk_enable and clk_disable are functional & control gating
  20. * rate - inherits rate from parent. No clk_set_rate support
  21. * parent - fixed parent. No clk_set_parent support
  22. */
  23. static inline u32 clk_gate_readl(struct clk_gate *gate)
  24. {
  25. if (gate->flags & CLK_GATE_BIG_ENDIAN)
  26. return ioread32be(gate->reg);
  27. return readl(gate->reg);
  28. }
  29. static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
  30. {
  31. if (gate->flags & CLK_GATE_BIG_ENDIAN)
  32. iowrite32be(val, gate->reg);
  33. else
  34. writel(val, gate->reg);
  35. }
  36. /*
  37. * It works on following logic:
  38. *
  39. * For enabling clock, enable = 1
  40. * set2dis = 1 -> clear bit -> set = 0
  41. * set2dis = 0 -> set bit -> set = 1
  42. *
  43. * For disabling clock, enable = 0
  44. * set2dis = 1 -> set bit -> set = 1
  45. * set2dis = 0 -> clear bit -> set = 0
  46. *
  47. * So, result is always: enable xor set2dis.
  48. */
  49. static void clk_gate_endisable(struct clk_hw *hw, int enable)
  50. {
  51. struct clk_gate *gate = to_clk_gate(hw);
  52. int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
  53. unsigned long flags;
  54. u32 reg;
  55. set ^= enable;
  56. if (gate->lock)
  57. spin_lock_irqsave(gate->lock, flags);
  58. else
  59. __acquire(gate->lock);
  60. if (gate->flags & CLK_GATE_HIWORD_MASK) {
  61. reg = BIT(gate->bit_idx + 16);
  62. if (set)
  63. reg |= BIT(gate->bit_idx);
  64. } else {
  65. reg = clk_gate_readl(gate);
  66. if (set)
  67. reg |= BIT(gate->bit_idx);
  68. else
  69. reg &= ~BIT(gate->bit_idx);
  70. }
  71. clk_gate_writel(gate, reg);
  72. if (gate->lock)
  73. spin_unlock_irqrestore(gate->lock, flags);
  74. else
  75. __release(gate->lock);
  76. }
  77. static int clk_gate_enable(struct clk_hw *hw)
  78. {
  79. clk_gate_endisable(hw, 1);
  80. return 0;
  81. }
  82. static void clk_gate_disable(struct clk_hw *hw)
  83. {
  84. clk_gate_endisable(hw, 0);
  85. }
  86. int clk_gate_is_enabled(struct clk_hw *hw)
  87. {
  88. u32 reg;
  89. struct clk_gate *gate = to_clk_gate(hw);
  90. reg = clk_gate_readl(gate);
  91. /* if a set bit disables this clk, flip it before masking */
  92. if (gate->flags & CLK_GATE_SET_TO_DISABLE)
  93. reg ^= BIT(gate->bit_idx);
  94. reg &= BIT(gate->bit_idx);
  95. return reg ? 1 : 0;
  96. }
  97. EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
  98. const struct clk_ops clk_gate_ops = {
  99. .enable = clk_gate_enable,
  100. .disable = clk_gate_disable,
  101. .is_enabled = clk_gate_is_enabled,
  102. };
  103. EXPORT_SYMBOL_GPL(clk_gate_ops);
  104. struct clk_hw *__clk_hw_register_gate(struct device *dev,
  105. struct device_node *np, const char *name,
  106. const char *parent_name, const struct clk_hw *parent_hw,
  107. const struct clk_parent_data *parent_data,
  108. unsigned long flags,
  109. void __iomem *reg, u8 bit_idx,
  110. u8 clk_gate_flags, spinlock_t *lock)
  111. {
  112. struct clk_gate *gate;
  113. struct clk_hw *hw;
  114. struct clk_init_data init = {};
  115. int ret = -EINVAL;
  116. if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
  117. if (bit_idx > 15) {
  118. pr_err("gate bit exceeds LOWORD field\n");
  119. return ERR_PTR(-EINVAL);
  120. }
  121. }
  122. /* allocate the gate */
  123. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  124. if (!gate)
  125. return ERR_PTR(-ENOMEM);
  126. init.name = name;
  127. init.ops = &clk_gate_ops;
  128. init.flags = flags;
  129. init.parent_names = parent_name ? &parent_name : NULL;
  130. init.parent_hws = parent_hw ? &parent_hw : NULL;
  131. init.parent_data = parent_data;
  132. if (parent_name || parent_hw || parent_data)
  133. init.num_parents = 1;
  134. else
  135. init.num_parents = 0;
  136. /* struct clk_gate assignments */
  137. gate->reg = reg;
  138. gate->bit_idx = bit_idx;
  139. gate->flags = clk_gate_flags;
  140. gate->lock = lock;
  141. gate->hw.init = &init;
  142. hw = &gate->hw;
  143. if (dev || !np)
  144. ret = clk_hw_register(dev, hw);
  145. else if (np)
  146. ret = of_clk_hw_register(np, hw);
  147. if (ret) {
  148. kfree(gate);
  149. hw = ERR_PTR(ret);
  150. }
  151. return hw;
  152. }
  153. EXPORT_SYMBOL_GPL(__clk_hw_register_gate);
  154. struct clk *clk_register_gate(struct device *dev, const char *name,
  155. const char *parent_name, unsigned long flags,
  156. void __iomem *reg, u8 bit_idx,
  157. u8 clk_gate_flags, spinlock_t *lock)
  158. {
  159. struct clk_hw *hw;
  160. hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
  161. bit_idx, clk_gate_flags, lock);
  162. if (IS_ERR(hw))
  163. return ERR_CAST(hw);
  164. return hw->clk;
  165. }
  166. EXPORT_SYMBOL_GPL(clk_register_gate);
  167. void clk_unregister_gate(struct clk *clk)
  168. {
  169. struct clk_gate *gate;
  170. struct clk_hw *hw;
  171. hw = __clk_get_hw(clk);
  172. if (!hw)
  173. return;
  174. gate = to_clk_gate(hw);
  175. clk_unregister(clk);
  176. kfree(gate);
  177. }
  178. EXPORT_SYMBOL_GPL(clk_unregister_gate);
  179. void clk_hw_unregister_gate(struct clk_hw *hw)
  180. {
  181. struct clk_gate *gate;
  182. gate = to_clk_gate(hw);
  183. clk_hw_unregister(hw);
  184. kfree(gate);
  185. }
  186. EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);