clk-efm32gg.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Pengutronix
  4. * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
  5. */
  6. #include <linux/io.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/slab.h>
  11. #include <dt-bindings/clock/efm32-cmu.h>
  12. #define CMU_HFPERCLKEN0 0x44
  13. #define CMU_MAX_CLKS 37
  14. static struct clk_hw_onecell_data *clk_data;
  15. static void __init efm32gg_cmu_init(struct device_node *np)
  16. {
  17. int i;
  18. void __iomem *base;
  19. struct clk_hw **hws;
  20. clk_data = kzalloc(struct_size(clk_data, hws, CMU_MAX_CLKS),
  21. GFP_KERNEL);
  22. if (!clk_data)
  23. return;
  24. hws = clk_data->hws;
  25. for (i = 0; i < CMU_MAX_CLKS; ++i)
  26. hws[i] = ERR_PTR(-ENOENT);
  27. base = of_iomap(np, 0);
  28. if (!base) {
  29. pr_warn("Failed to map address range for efm32gg,cmu node\n");
  30. return;
  31. }
  32. hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0,
  33. 48000000);
  34. hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0",
  35. "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
  36. hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1",
  37. "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
  38. hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2",
  39. "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
  40. hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0",
  41. "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
  42. hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1",
  43. "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
  44. hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0",
  45. "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
  46. hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1",
  47. "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
  48. hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2",
  49. "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
  50. hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3",
  51. "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
  52. hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0",
  53. "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
  54. hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1",
  55. "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
  56. hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0",
  57. "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
  58. hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1",
  59. "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
  60. hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO",
  61. "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
  62. hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP",
  63. "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
  64. hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS",
  65. "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
  66. hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0",
  67. "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
  68. hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
  69. "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
  70. of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
  71. }
  72. CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);